Commit bcee502c authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Simon Horman
Browse files

arm64: dts: renesas: r8a77980: add RWDT support 



Describe RWDT in the R8A77980 SoC device tree.

Enable RWDT on the Condor and V3H Starter Kit boards.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: default avatarVladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 5b394b2d

arch/arm64/boot/dts/renesas/r8a77980-condor.dts

+5 −0
Original line number Diff line number Diff line
@@ -156,6 +156,11 @@ 
	};

};



&rwdt {

	timeout-sec = <60>;

	status = "okay";

};



&scif0 {

	pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;

	pinctrl-names = "default";

arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts

+5 −0
Original line number Diff line number Diff line
@@ -71,6 +71,11 @@ 
	};

};



&rwdt {

	timeout-sec = <60>;

	status = "okay";

};



&scif0 {

	pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;

	pinctrl-names = "default";

arch/arm64/boot/dts/renesas/r8a77980.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -118,6 +118,16 @@ 
		#size-cells = <2>;

		ranges;



		rwdt: watchdog@e6020000 {

			compatible = "renesas,r8a77980-wdt",

				     "renesas,rcar-gen3-wdt";

			reg = <0 0xe6020000 0 0x0c>;

			clocks = <&cpg CPG_MOD 402>;

			power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;

			resets = <&cpg 402>;

			status = "disabled";

		};



		gpio0: gpio@e6050000 {

			compatible = "renesas,gpio-r8a77980",

				     "renesas,rcar-gen3-gpio";

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