Commit bcd17397 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_5.2_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull a few more MIPS updates from Paul Burton:
 "Some SGI IP27 specific PCI rework and a batch of fixes:

   - A build fix for BMIPS5000 configurations with
     CONFIG_HW_PERF_EVENTS=y, which also neatly removes some #ifdefery.

   - A fix to report supported ISAs correctly on older Ingenic SoCs
     which incorrectly indicate MIPSr2 support in their cop0 Config
     register.

   - Some PCI modernization for SGI IP27 systems as part of ongoing work
     to support some other SGI systems.

   - A fix allowing use of appended DTB files with generic kernels.

   - DMA mask fixes for SGI IP22 & Alchemy systems"

* tag 'mips_5.2_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: Alchemy: add DMA masks for on-chip ethernet
  MIPS: SGI-IP22: provide missing dma_mask/coherent_dma_mask
  generic: fix appended dtb support
  MIPS: SGI-IP27: abstract chipset irq from bridge
  MIPS: SGI-IP27: use generic PCI driver
  MIPS: Fix Ingenic SoCs sometimes reporting wrong ISA
  MIPS: perf: Fix build with CONFIG_CPU_BMIPS5000 enabled
parents b0bb1269 b1e479e3

arch/mips/Kconfig

+6 −0
Original line number Diff line number Diff line
@@ -674,7 +674,10 @@ config SGI_IP27 
	select SYS_HAS_EARLY_PRINTK

	select HAVE_PCI

	select IRQ_MIPS_CPU

	select IRQ_DOMAIN_HIERARCHY

	select NR_CPUS_DEFAULT_64

	select PCI_DRIVERS_GENERIC

	select PCI_XTALK_BRIDGE

	select SYS_HAS_CPU_R10000

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN
@@ -1241,6 +1244,9 @@ config IRQ_GT641XX 
config PCI_GT64XXX_PCI0

	bool



config PCI_XTALK_BRIDGE

	bool



config NO_EXCEPT_FILL

	bool

arch/mips/alchemy/common/platform.c

+14 −8
Original line number Diff line number Diff line
@@ -131,9 +131,7 @@ static void __init alchemy_setup_uarts(int ctype) 
}





/* The dmamask must be set for OHCI/EHCI to work */

static u64 alchemy_ohci_dmamask = DMA_BIT_MASK(32);

static u64 __maybe_unused alchemy_ehci_dmamask = DMA_BIT_MASK(32);

static u64 alchemy_all_dmamask = DMA_BIT_MASK(32);



/* Power on callback for the ehci platform driver */

static int alchemy_ehci_power_on(struct platform_device *pdev)
@@ -231,7 +229,7 @@ static void __init alchemy_setup_usb(int ctype) 
	res[1].flags = IORESOURCE_IRQ;

	pdev->name = "ohci-platform";

	pdev->id = 0;

	pdev->dev.dma_mask = &alchemy_ohci_dmamask;

	pdev->dev.dma_mask = &alchemy_all_dmamask;

	pdev->dev.platform_data = &alchemy_ohci_pdata;



	if (platform_device_register(pdev))
@@ -251,7 +249,7 @@ static void __init alchemy_setup_usb(int ctype) 
		res[1].flags = IORESOURCE_IRQ;

		pdev->name = "ehci-platform";

		pdev->id = 0;

		pdev->dev.dma_mask = &alchemy_ehci_dmamask;

		pdev->dev.dma_mask = &alchemy_all_dmamask;

		pdev->dev.platform_data = &alchemy_ehci_pdata;



		if (platform_device_register(pdev))
@@ -271,7 +269,7 @@ static void __init alchemy_setup_usb(int ctype) 
		res[1].flags = IORESOURCE_IRQ;

		pdev->name = "ohci-platform";

		pdev->id = 1;

		pdev->dev.dma_mask = &alchemy_ohci_dmamask;

		pdev->dev.dma_mask = &alchemy_all_dmamask;

		pdev->dev.platform_data = &alchemy_ohci_pdata;



		if (platform_device_register(pdev))
@@ -338,7 +336,11 @@ static struct platform_device au1xxx_eth0_device = { 
	.name		= "au1000-eth",

	.id		= 0,

	.num_resources	= MAC_RES_COUNT,

	.dev.platform_data = &au1xxx_eth0_platform_data,

	.dev = {

		.dma_mask               = &alchemy_all_dmamask,

		.coherent_dma_mask      = DMA_BIT_MASK(32),

		.platform_data          = &au1xxx_eth0_platform_data,

	},

};



static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = {
@@ -370,7 +372,11 @@ static struct platform_device au1xxx_eth1_device = { 
	.name		= "au1000-eth",

	.id		= 1,

	.num_resources	= MAC_RES_COUNT,

	.dev.platform_data = &au1xxx_eth1_platform_data,

	.dev = {

		.dma_mask               = &alchemy_all_dmamask,

		.coherent_dma_mask      = DMA_BIT_MASK(32),

		.platform_data          = &au1xxx_eth1_platform_data,

	},

};



void __init au1xxx_override_eth_cfg(unsigned int port,

arch/mips/generic/init.c

+2 −2
Original line number Diff line number Diff line
@@ -43,14 +43,14 @@ void __init *plat_get_fdt(void) 
		/* Already set up */

		return (void *)fdt;



	if ((fw_arg0 == -2) && !fdt_check_header((void *)fw_arg1)) {

	if ((fw_arg0 == -2) && !fdt_check_header((void *)fw_passed_dtb)) {

		/*

		 * We booted using the UHI boot protocol, so we have been

		 * provided with the appropriate device tree for the board.

		 * Make use of it & search for any machine struct based upon

		 * the root compatible string.

		 */

		fdt = (void *)fw_arg1;

		fdt = (void *)fw_passed_dtb;



		for_each_mips_machine(check_mach) {

			match = mips_machine_is_compatible(check_mach, fdt);

arch/mips/include/asm/mach-ip27/topology.h

+1 −10
Original line number Diff line number Diff line
@@ -7,18 +7,9 @@ 
#include <asm/mmzone.h>



struct cpuinfo_ip27 {

//	cpuid_t		p_cpuid;	/* PROM assigned cpuid */

	cnodeid_t	p_nodeid;	/* my node ID in compact-id-space */

	nasid_t		p_nasid;	/* my node ID in numa-as-id-space */

	unsigned char	p_slice;	/* Physical position on node board */

#if 0

	unsigned long		loops_per_sec;

	unsigned long		ipi_count;

	unsigned long		irq_attempt[NR_IRQS];

	unsigned long		smp_local_irq_count;

	unsigned long		prof_multiplier;

	unsigned long		prof_counter;

#endif

};



extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
@@ -30,7 +21,7 @@ extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS]; 
struct pci_bus;

extern int pcibus_to_node(struct pci_bus *);



#define cpumask_of_pcibus(bus)	(cpu_online_mask)

#define cpumask_of_pcibus(bus)	(cpumask_of_node(pcibus_to_node(bus)))



extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];

arch/mips/include/asm/pci/bridge.h

+4 −10
Original line number Diff line number Diff line
@@ -801,15 +801,13 @@ struct bridge_err_cmdword { 
#define PCI64_ATTR_RMF_SHFT	48



struct bridge_controller {

	struct pci_controller	pc;

	struct resource		mem;

	struct resource		io;

	struct resource		busn;

	struct bridge_regs	*base;

	nasid_t			nasid;

	unsigned int		widget_id;

	u64			baddr;

	unsigned long		baddr;

	unsigned long		intr_addr;

	struct irq_domain	*domain;

	unsigned int		pci_int[8];

	nasid_t			nasid;

};



#define BRIDGE_CONTROLLER(bus) \
@@ -822,8 +820,4 @@ struct bridge_controller { 
#define bridge_clr(bc, reg, val)	\

	__raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)



extern int request_bridge_irq(struct bridge_controller *bc, int pin);



extern struct pci_ops bridge_pci_ops;



#endif /* _ASM_PCI_BRIDGE_H */

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