igc: Add PHY power management control

/* PHY Status Register */

#define MII_SR_LINK_STATUS	0x0004 /* Link Status 1 = link */

#define MII_SR_AUTONEG_COMPLETE	0x0020 /* Auto Neg Complete */

#define IGC_PHY_RST_COMP	0x0100 /* Internal PHY reset completion */

/* PHY 1000 MII Register/Bit Definitions */

/* PHY Registers defined by IEEE */

s32 igc_phy_hw_reset(struct igc_hw *hw)

{

	struct igc_phy_info *phy = &hw->phy;

	u32 phpm = 0, timeout = 10000;

	s32  ret_val;

	u32 ctrl;

	if (ret_val)

		goto out;

	phpm = rd32(IGC_I225_PHPM);

	ctrl = rd32(IGC_CTRL);

	wr32(IGC_CTRL, ctrl | IGC_CTRL_PHY_RST);

	wrfl();

	wr32(IGC_CTRL, ctrl);

	wrfl();

	usleep_range(1500, 2000);

	/* SW should guarantee 100us for the completion of the PHY reset */

	usleep_range(100, 150);

	do {

		phpm = rd32(IGC_I225_PHPM);

		timeout--;

		udelay(1);

	} while (!(phpm & IGC_PHY_RST_COMP) && timeout);

	if (!timeout)

		hw_dbg("Timeout is expired after a phy reset\n");

	usleep_range(100, 150);

	phy->ops.release(hw);

#define IGC_MDIC		0x00020  /* MDI Control - RW */

#define IGC_MDICNFG		0x00E04  /* MDC/MDIO Configuration - RW */

#define IGC_CONNSW		0x00034  /* Copper/Fiber switch control - RW */

#define IGC_I225_PHPM		0x00E14  /* I225 PHY Power Management */

/* Internal Packet Buffer Size Registers */

#define IGC_RXPBS		0x02404  /* Rx Packet Buffer Size - RW */