Commit bcacd6f7 authored Feb 11, 2020 by Fabio Estevam Committed by Shawn Guo Feb 17, 2020

clk: imx8mm: Fix the CLKO1 source select list



The CLKO1 clock source select list is the following as per the i.MX8MM
Reference Manual (put in increasing order):

000 - 24M_REF_CLK
001 - SYSTEM_PLL1_CLK
010 - None
011 - SYSTEM_PLL1_DIV4
100 - AUDIO_PLL2_CLK
101 - SYSTEM_PLL2_DIV2
110 - VPU_PLL_CLK
111 - SYSTEM_PLL1_DIV10

Fix it accordingly.

Fixes: ba5625c3 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

parent 33db2ce7

drivers/clk/imx/clk-imx8mm.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -283,8 +283,8 @@ static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_8

		static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };

		static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", "sys_pll1_200m", "audio_pll2_out",
		"vpu_pll", "sys_pll1_80m", };
		static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "sys_pll1_200m",
		"audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", };

		static struct clk_hw_onecell_data *clk_hw_data;
		static struct clk_hw **hws;

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