Commit bca1a5c0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf updates from Ingo Molnar:
 "The biggest changes are Intel Nehalem-EX PMU uncore support, uprobes
  updates/cleanups/fixes from Oleg and diverse tooling updates (mostly
  fixes) now that Arnaldo is back from vacation."

* 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (40 commits)
  uprobes: __replace_page() needs munlock_vma_page()
  uprobes: Rename vma_address() and make it return "unsigned long"
  uprobes: Fix register_for_each_vma()->vma_address() check
  uprobes: Introduce vaddr_to_offset(vma, vaddr)
  uprobes: Teach build_probe_list() to consider the range
  uprobes: Remove insert_vm_struct()->uprobe_mmap()
  uprobes: Remove copy_vma()->uprobe_mmap()
  uprobes: Fix overflow in vma_address()/find_active_uprobe()
  uprobes: Suppress uprobe_munmap() from mmput()
  uprobes: Uprobe_mmap/munmap needs list_for_each_entry_safe()
  uprobes: Clean up and document write_opcode()->lock_page(old_page)
  uprobes: Kill write_opcode()->lock_page(new_page)
  uprobes: __replace_page() should not use page_address_in_vma()
  uprobes: Don't recheck vma/f_mapping in write_opcode()
  perf/x86: Fix missing struct before structure name
  perf/x86: Fix format definition of SNB-EP uncore QPI box
  perf/x86: Make bitfield unsigned
  perf/x86: Fix LLC-* and node-* events on Intel SandyBridge
  perf/x86: Add Intel Nehalem-EX uncore support
  perf/x86: Fix typo in format definition of uncore PCU filter
  ...
parents ec7a19bf 194f8dcb

arch/x86/include/asm/perf_event.h

+1 −1
Original line number Diff line number Diff line
@@ -234,7 +234,7 @@ extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr); 
extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);

extern void perf_check_microcode(void);

#else

static inline perf_guest_switch_msr *perf_guest_get_msrs(int *nr)

static inline struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)

{

	*nr = 0;

	return NULL;

arch/x86/kernel/cpu/perf_event.h

+1 −1
Original line number Diff line number Diff line
@@ -374,7 +374,7 @@ struct x86_pmu { 
	/*

	 * Intel DebugStore bits

	 */

	int		bts		:1,

	unsigned int	bts		:1,

			bts_active	:1,

			pebs		:1,

			pebs_active	:1,

arch/x86/kernel/cpu/perf_event_intel.c

+86 −6
Original line number Diff line number Diff line
@@ -138,6 +138,84 @@ static u64 intel_pmu_event_map(int hw_event) 
	return intel_perfmon_event_map[hw_event];

}



#define SNB_DMND_DATA_RD	(1ULL << 0)

#define SNB_DMND_RFO		(1ULL << 1)

#define SNB_DMND_IFETCH		(1ULL << 2)

#define SNB_DMND_WB		(1ULL << 3)

#define SNB_PF_DATA_RD		(1ULL << 4)

#define SNB_PF_RFO		(1ULL << 5)

#define SNB_PF_IFETCH		(1ULL << 6)

#define SNB_LLC_DATA_RD		(1ULL << 7)

#define SNB_LLC_RFO		(1ULL << 8)

#define SNB_LLC_IFETCH		(1ULL << 9)

#define SNB_BUS_LOCKS		(1ULL << 10)

#define SNB_STRM_ST		(1ULL << 11)

#define SNB_OTHER		(1ULL << 15)

#define SNB_RESP_ANY		(1ULL << 16)

#define SNB_NO_SUPP		(1ULL << 17)

#define SNB_LLC_HITM		(1ULL << 18)

#define SNB_LLC_HITE		(1ULL << 19)

#define SNB_LLC_HITS		(1ULL << 20)

#define SNB_LLC_HITF		(1ULL << 21)

#define SNB_LOCAL		(1ULL << 22)

#define SNB_REMOTE		(0xffULL << 23)

#define SNB_SNP_NONE		(1ULL << 31)

#define SNB_SNP_NOT_NEEDED	(1ULL << 32)

#define SNB_SNP_MISS		(1ULL << 33)

#define SNB_NO_FWD		(1ULL << 34)

#define SNB_SNP_FWD		(1ULL << 35)

#define SNB_HITM		(1ULL << 36)

#define SNB_NON_DRAM		(1ULL << 37)



#define SNB_DMND_READ		(SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)

#define SNB_DMND_WRITE		(SNB_DMND_RFO|SNB_LLC_RFO)

#define SNB_DMND_PREFETCH	(SNB_PF_DATA_RD|SNB_PF_RFO)



#define SNB_SNP_ANY		(SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \

				 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \

				 SNB_HITM)



#define SNB_DRAM_ANY		(SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)

#define SNB_DRAM_REMOTE		(SNB_REMOTE|SNB_SNP_ANY)



#define SNB_L3_ACCESS		SNB_RESP_ANY

#define SNB_L3_MISS		(SNB_DRAM_ANY|SNB_NON_DRAM)



static __initconst const u64 snb_hw_cache_extra_regs

				[PERF_COUNT_HW_CACHE_MAX]

				[PERF_COUNT_HW_CACHE_OP_MAX]

				[PERF_COUNT_HW_CACHE_RESULT_MAX] =

{

 [ C(LL  ) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,

		[ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,

		[ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,

		[ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,

	},

 },

 [ C(NODE) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,

		[ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,

		[ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,

		[ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,

	},

 },

};



static __initconst const u64 snb_hw_cache_event_ids

				[PERF_COUNT_HW_CACHE_MAX]

				[PERF_COUNT_HW_CACHE_OP_MAX]
@@ -235,16 +313,16 @@ static __initconst const u64 snb_hw_cache_event_ids 
 },

 [ C(NODE) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

		[ C(RESULT_ACCESS) ] = 0x01b7,

		[ C(RESULT_MISS)   ] = 0x01b7,

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

		[ C(RESULT_ACCESS) ] = 0x01b7,

		[ C(RESULT_MISS)   ] = 0x01b7,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = -1,

		[ C(RESULT_MISS)   ] = -1,

		[ C(RESULT_ACCESS) ] = 0x01b7,

		[ C(RESULT_MISS)   ] = 0x01b7,

	},

 },
@@ -1964,6 +2042,8 @@ __init int intel_pmu_init(void) 
	case 58: /* IvyBridge */

		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));

		memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,

		       sizeof(hw_cache_extra_regs));



		intel_pmu_lbr_init_snb();

arch/x86/kernel/cpu/perf_event_intel_uncore.c

+1286 −236

File changed.

Preview size limit exceeded, changes collapsed.

arch/x86/kernel/cpu/perf_event_intel_uncore.h

+202 −5
Original line number Diff line number Diff line
@@ -5,8 +5,6 @@ 
#include "perf_event.h"



#define UNCORE_PMU_NAME_LEN		32

#define UNCORE_BOX_HASH_SIZE		8



#define UNCORE_PMU_HRTIMER_INTERVAL	(60 * NSEC_PER_SEC)



#define UNCORE_FIXED_EVENT		0xff
@@ -115,6 +113,10 @@ 
				 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \

				 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)



#define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK	\

				(SNBEP_PMON_RAW_EVENT_MASK | \

				 SNBEP_PMON_CTL_EV_SEL_EXT)



/* SNB-EP pci control register */

#define SNBEP_PCI_PMON_BOX_CTL			0xf4

#define SNBEP_PCI_PMON_CTL0			0xd8
@@ -158,6 +160,193 @@ 
#define SNBEP_PCU_MSR_CORE_C3_CTR		0x3fc

#define SNBEP_PCU_MSR_CORE_C6_CTR		0x3fd



/* NHM-EX event control */

#define NHMEX_PMON_CTL_EV_SEL_MASK	0x000000ff

#define NHMEX_PMON_CTL_UMASK_MASK	0x0000ff00

#define NHMEX_PMON_CTL_EN_BIT0		(1 << 0)

#define NHMEX_PMON_CTL_EDGE_DET		(1 << 18)

#define NHMEX_PMON_CTL_PMI_EN		(1 << 20)

#define NHMEX_PMON_CTL_EN_BIT22		(1 << 22)

#define NHMEX_PMON_CTL_INVERT		(1 << 23)

#define NHMEX_PMON_CTL_TRESH_MASK	0xff000000

#define NHMEX_PMON_RAW_EVENT_MASK	(NHMEX_PMON_CTL_EV_SEL_MASK | \

					 NHMEX_PMON_CTL_UMASK_MASK | \

					 NHMEX_PMON_CTL_EDGE_DET | \

					 NHMEX_PMON_CTL_INVERT | \

					 NHMEX_PMON_CTL_TRESH_MASK)



/* NHM-EX Ubox */

#define NHMEX_U_MSR_PMON_GLOBAL_CTL		0xc00

#define NHMEX_U_MSR_PMON_CTR			0xc11

#define NHMEX_U_MSR_PMON_EV_SEL			0xc10



#define NHMEX_U_PMON_GLOBAL_EN			(1 << 0)

#define NHMEX_U_PMON_GLOBAL_PMI_CORE_SEL	0x0000001e

#define NHMEX_U_PMON_GLOBAL_EN_ALL		(1 << 28)

#define NHMEX_U_PMON_GLOBAL_RST_ALL		(1 << 29)

#define NHMEX_U_PMON_GLOBAL_FRZ_ALL		(1 << 31)



#define NHMEX_U_PMON_RAW_EVENT_MASK		\

		(NHMEX_PMON_CTL_EV_SEL_MASK |	\

		 NHMEX_PMON_CTL_EDGE_DET)



/* NHM-EX Cbox */

#define NHMEX_C0_MSR_PMON_GLOBAL_CTL		0xd00

#define NHMEX_C0_MSR_PMON_CTR0			0xd11

#define NHMEX_C0_MSR_PMON_EV_SEL0		0xd10

#define NHMEX_C_MSR_OFFSET			0x20



/* NHM-EX Bbox */

#define NHMEX_B0_MSR_PMON_GLOBAL_CTL		0xc20

#define NHMEX_B0_MSR_PMON_CTR0			0xc31

#define NHMEX_B0_MSR_PMON_CTL0			0xc30

#define NHMEX_B_MSR_OFFSET			0x40

#define NHMEX_B0_MSR_MATCH			0xe45

#define NHMEX_B0_MSR_MASK			0xe46

#define NHMEX_B1_MSR_MATCH			0xe4d

#define NHMEX_B1_MSR_MASK			0xe4e



#define NHMEX_B_PMON_CTL_EN			(1 << 0)

#define NHMEX_B_PMON_CTL_EV_SEL_SHIFT		1

#define NHMEX_B_PMON_CTL_EV_SEL_MASK		\

		(0x1f << NHMEX_B_PMON_CTL_EV_SEL_SHIFT)

#define NHMEX_B_PMON_CTR_SHIFT		6

#define NHMEX_B_PMON_CTR_MASK		\

		(0x3 << NHMEX_B_PMON_CTR_SHIFT)

#define NHMEX_B_PMON_RAW_EVENT_MASK		\

		(NHMEX_B_PMON_CTL_EV_SEL_MASK | \

		 NHMEX_B_PMON_CTR_MASK)



/* NHM-EX Sbox */

#define NHMEX_S0_MSR_PMON_GLOBAL_CTL		0xc40

#define NHMEX_S0_MSR_PMON_CTR0			0xc51

#define NHMEX_S0_MSR_PMON_CTL0			0xc50

#define NHMEX_S_MSR_OFFSET			0x80

#define NHMEX_S0_MSR_MM_CFG			0xe48

#define NHMEX_S0_MSR_MATCH			0xe49

#define NHMEX_S0_MSR_MASK			0xe4a

#define NHMEX_S1_MSR_MM_CFG			0xe58

#define NHMEX_S1_MSR_MATCH			0xe59

#define NHMEX_S1_MSR_MASK			0xe5a



#define NHMEX_S_PMON_MM_CFG_EN			(0x1ULL << 63)



/* NHM-EX Mbox */

#define NHMEX_M0_MSR_GLOBAL_CTL			0xca0

#define NHMEX_M0_MSR_PMU_DSP			0xca5

#define NHMEX_M0_MSR_PMU_ISS			0xca6

#define NHMEX_M0_MSR_PMU_MAP			0xca7

#define NHMEX_M0_MSR_PMU_MSC_THR		0xca8

#define NHMEX_M0_MSR_PMU_PGT			0xca9

#define NHMEX_M0_MSR_PMU_PLD			0xcaa

#define NHMEX_M0_MSR_PMU_ZDP_CTL_FVC		0xcab

#define NHMEX_M0_MSR_PMU_CTL0			0xcb0

#define NHMEX_M0_MSR_PMU_CNT0			0xcb1

#define NHMEX_M_MSR_OFFSET			0x40

#define NHMEX_M0_MSR_PMU_MM_CFG			0xe54

#define NHMEX_M1_MSR_PMU_MM_CFG			0xe5c



#define NHMEX_M_PMON_MM_CFG_EN			(1ULL << 63)

#define NHMEX_M_PMON_ADDR_MATCH_MASK		0x3ffffffffULL

#define NHMEX_M_PMON_ADDR_MASK_MASK		0x7ffffffULL

#define NHMEX_M_PMON_ADDR_MASK_SHIFT		34



#define NHMEX_M_PMON_CTL_EN			(1 << 0)

#define NHMEX_M_PMON_CTL_PMI_EN			(1 << 1)

#define NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT	2

#define NHMEX_M_PMON_CTL_COUNT_MODE_MASK	\

	(0x3 << NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT)

#define NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT	4

#define NHMEX_M_PMON_CTL_STORAGE_MODE_MASK	\

	(0x3 << NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT)

#define NHMEX_M_PMON_CTL_WRAP_MODE		(1 << 6)

#define NHMEX_M_PMON_CTL_FLAG_MODE		(1 << 7)

#define NHMEX_M_PMON_CTL_INC_SEL_SHIFT		9

#define NHMEX_M_PMON_CTL_INC_SEL_MASK		\

	(0x1f << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)

#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT	19

#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK	\

	(0x7 << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT)

#define NHMEX_M_PMON_RAW_EVENT_MASK			\

		(NHMEX_M_PMON_CTL_COUNT_MODE_MASK |	\

		 NHMEX_M_PMON_CTL_STORAGE_MODE_MASK |	\

		 NHMEX_M_PMON_CTL_WRAP_MODE |		\

		 NHMEX_M_PMON_CTL_FLAG_MODE |		\

		 NHMEX_M_PMON_CTL_INC_SEL_MASK |	\

		 NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK)





#define NHMEX_M_PMON_ZDP_CTL_FVC_FVID_MASK	0x1f

#define NHMEX_M_PMON_ZDP_CTL_FVC_BCMD_MASK	(0x7 << 5)

#define NHMEX_M_PMON_ZDP_CTL_FVC_RSP_MASK	(0x7 << 8)

#define NHMEX_M_PMON_ZDP_CTL_FVC_PBOX_INIT_ERR	(1 << 23)

#define NHMEX_M_PMON_ZDP_CTL_FVC_MASK			\

		(NHMEX_M_PMON_ZDP_CTL_FVC_FVID_MASK |	\

		 NHMEX_M_PMON_ZDP_CTL_FVC_BCMD_MASK |	\

		 NHMEX_M_PMON_ZDP_CTL_FVC_RSP_MASK  |	\

		 NHMEX_M_PMON_ZDP_CTL_FVC_PBOX_INIT_ERR)

#define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n)	(0x7 << (11 + 3 * (n)))



/*

 * use the 9~13 bits to select event If the 7th bit is not set,

 * otherwise use the 19~21 bits to select event.

 */

#define MBOX_INC_SEL(x) ((x) << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)

#define MBOX_SET_FLAG_SEL(x) (((x) << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT) | \

				NHMEX_M_PMON_CTL_FLAG_MODE)

#define MBOX_INC_SEL_MASK (NHMEX_M_PMON_CTL_INC_SEL_MASK | \

			   NHMEX_M_PMON_CTL_FLAG_MODE)

#define MBOX_SET_FLAG_SEL_MASK (NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK | \

				NHMEX_M_PMON_CTL_FLAG_MODE)

#define MBOX_INC_SEL_EXTAR_REG(c, r) \

		EVENT_EXTRA_REG(MBOX_INC_SEL(c), NHMEX_M0_MSR_PMU_##r, \

				MBOX_INC_SEL_MASK, (u64)-1, NHMEX_M_##r)

#define MBOX_SET_FLAG_SEL_EXTRA_REG(c, r) \

		EVENT_EXTRA_REG(MBOX_SET_FLAG_SEL(c), NHMEX_M0_MSR_PMU_##r, \

				MBOX_SET_FLAG_SEL_MASK, \

				(u64)-1, NHMEX_M_##r)



/* NHM-EX Rbox */

#define NHMEX_R_MSR_GLOBAL_CTL			0xe00

#define NHMEX_R_MSR_PMON_CTL0			0xe10

#define NHMEX_R_MSR_PMON_CNT0			0xe11

#define NHMEX_R_MSR_OFFSET			0x20



#define NHMEX_R_MSR_PORTN_QLX_CFG(n)		\

		((n) < 4 ? (0xe0c + (n)) : (0xe2c + (n) - 4))

#define NHMEX_R_MSR_PORTN_IPERF_CFG0(n)		(0xe04 + (n))

#define NHMEX_R_MSR_PORTN_IPERF_CFG1(n)		(0xe24 + (n))

#define NHMEX_R_MSR_PORTN_XBR_OFFSET(n)		\

		(((n) < 4 ? 0 : 0x10) + (n) * 4)

#define NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n)	\

		(0xe60 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))

#define NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(n)	\

		(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 1)

#define NHMEX_R_MSR_PORTN_XBR_SET1_MASK(n)	\

		(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 2)

#define NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n)	\

		(0xe70 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))

#define NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(n)	\

		(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 1)

#define NHMEX_R_MSR_PORTN_XBR_SET2_MASK(n)	\

		(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 2)



#define NHMEX_R_PMON_CTL_EN			(1 << 0)

#define NHMEX_R_PMON_CTL_EV_SEL_SHIFT		1

#define NHMEX_R_PMON_CTL_EV_SEL_MASK		\

		(0x1f << NHMEX_R_PMON_CTL_EV_SEL_SHIFT)

#define NHMEX_R_PMON_CTL_PMI_EN			(1 << 6)

#define NHMEX_R_PMON_RAW_EVENT_MASK		NHMEX_R_PMON_CTL_EV_SEL_MASK



/* NHM-EX Wbox */

#define NHMEX_W_MSR_GLOBAL_CTL			0xc80

#define NHMEX_W_MSR_PMON_CNT0			0xc90

#define NHMEX_W_MSR_PMON_EVT_SEL0		0xc91

#define NHMEX_W_MSR_PMON_FIXED_CTR		0x394

#define NHMEX_W_MSR_PMON_FIXED_CTL		0x395



#define NHMEX_W_PMON_GLOBAL_FIXED_EN		(1ULL << 31)



struct intel_uncore_ops;

struct intel_uncore_pmu;

struct intel_uncore_box;
@@ -178,6 +367,7 @@ struct intel_uncore_type { 
	unsigned msr_offset;

	unsigned num_shared_regs:8;

	unsigned single_fixed:1;

	unsigned pair_ctr_ctl:1;

	struct event_constraint unconstrainted;

	struct event_constraint *constraints;

	struct intel_uncore_pmu *pmus;
@@ -213,7 +403,7 @@ struct intel_uncore_pmu { 


struct intel_uncore_extra_reg {

	raw_spinlock_t lock;

	u64 config1;

	u64 config, config1, config2;

	atomic_t ref;

};
@@ -323,14 +513,16 @@ unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box) 
static inline

unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)

{

	return idx + box->pmu->type->event_ctl +

	return box->pmu->type->event_ctl +

		(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +

		box->pmu->type->msr_offset * box->pmu->pmu_idx;

}



static inline

unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)

{

	return idx + box->pmu->type->perf_ctr +

	return box->pmu->type->perf_ctr +

		(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +

		box->pmu->type->msr_offset * box->pmu->pmu_idx;

}
@@ -422,3 +614,8 @@ static inline void uncore_box_init(struct intel_uncore_box *box) 
			box->pmu->type->ops->init_box(box);

	}

}



static inline bool uncore_box_is_fake(struct intel_uncore_box *box)

{

	return (box->phys_id < 0);

}

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