Unverified Commit bc88ad2e authored Jul 20, 2018 by Felix Fietkau Committed by Paul Burton Jul 20, 2018

MIPS: ath79: fix register address in ath79_ddr_wb_flush()



ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets
need to be a multiple of 4 in order to access the intended register.

Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Fixes: 24b0e3e8 ("MIPS: ath79: Improve the DDR controller interface")
Patchwork: https://patchwork.linux-mips.org/patch/19912/
Cc: Alban Bedel <albeu@free.fr>
Cc: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org # 4.2+

parent 38c0a74f

arch/mips/ath79/common.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);

		void ath79_ddr_wb_flush(u32 reg)
		{
		void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
		void __iomem flush_reg = ath79_ddr_wb_flush_base + (reg 4);

		/* Flush the DDR write buffer. */
		__raw_writel(0x1, flush_reg);

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