Commit bc71c096 authored by Linus Walleij's avatar Linus Walleij
Browse files

ARM: ux500: core U9540 support



This adds support for the U9540 variant of the U8500 series. This
is an application processor without internal modem. This is the
most basic part with ASIC ID, CPU-related fixes, IRQ list, register
ranges, timer, UART, and L2 cache setup. This is based on a patch
by Michel Jaouen which was rewritten to fit with the latest 3.3
kernel.

ChangeLog v1->v2: deleted the irqs-db9540.h file since we expect to
  migrate to using Device Tree for getting the IRQs to devices.
ChangeLog v2->v3: introduced a fixed virtual offset for the ROM
  as suggested by Arnd Bergmann.

Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarSebastien Pasdeloup <sebastien.pasdeloup-nonst@stericsson.com>
Signed-off-by: default avatarMichel Jaouen <michel.jaouen@stericsson.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 66f75a5d
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+1 −1
Original line number Diff line number Diff line
@@ -102,7 +102,7 @@ static int __init mop500_uib_init(void)
	struct i2c_adapter *i2c0;
	int ret;

	if (!cpu_is_u8500())
	if (!cpu_is_u8500_family())
		return -ENODEV;

	if (uib) {
+13 −3
Original line number Diff line number Diff line
@@ -36,9 +36,11 @@ static int __init ux500_l2x0_unlock(void)

static int __init ux500_l2x0_init(void)
{
	u32 aux_val = 0x3e000000;

	if (cpu_is_u5500())
		l2x0_base = __io_address(U5500_L2CC_BASE);
	else if (cpu_is_u8500())
	else if (cpu_is_u8500_family())
		l2x0_base = __io_address(U8500_L2CC_BASE);
	else
		ux500_unknown_soc();
@@ -46,11 +48,19 @@ static int __init ux500_l2x0_init(void)
	/* Unlock before init */
	ux500_l2x0_unlock();

	/* DB9540's L2 has 128KB way size */
	if (cpu_is_u9540())
		/* 128KB way size */
		aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
	else
		/* 64KB way size */
		aux_val |= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);

	/* 64KB way size, 8 way associativity, force WA */
	if (of_have_populated_dt())
		l2x0_of_init(0x3e060000, 0xc0000fff);
		l2x0_of_init(aux_val, 0xc0000fff);
	else
		l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
		l2x0_init(l2x0_base, aux_val, 0xc0000fff);

	/*
	 * We can't disable l2 as we are in non secure mode, currently
+1 −1
Original line number Diff line number Diff line
@@ -151,7 +151,7 @@ static unsigned long clk_mtu_get_rate(struct clk *clk)

	if (cpu_is_u5500())
		addr = __io_address(U5500_PRCMU_BASE);
	else if (cpu_is_u8500())
	else if (cpu_is_u8500_family())
		addr = __io_address(U8500_PRCMU_BASE);
	else
		ux500_unknown_soc();
+3 −3
Original line number Diff line number Diff line
@@ -34,8 +34,8 @@ static struct map_desc u8500_uart_io_desc[] __initdata = {
	__IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
};

static struct map_desc u8500_io_desc[] __initdata = {
/*  U8500 and U9540 common io_desc */
static struct map_desc u8500_common_io_desc[] __initdata = {
	/* SCU base also covers GIC CPU BASE and TWD with its 4K page */
	__IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
	__IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
@@ -66,7 +66,7 @@ void __init u8500_map_io(void)

	ux500_map_io();

	iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
	iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));

	_PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
}
+2 −2
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ void __init ux500_init_irq(void)
	if (cpu_is_u5500()) {
		dist_base = __io_address(U5500_GIC_DIST_BASE);
		cpu_base = __io_address(U5500_GIC_CPU_BASE);
	} else if (cpu_is_u8500()) {
	} else if (cpu_is_u8500_family()) {
		dist_base = __io_address(U8500_GIC_DIST_BASE);
		cpu_base = __io_address(U8500_GIC_CPU_BASE);
	} else
@@ -62,7 +62,7 @@ void __init ux500_init_irq(void)
	 */
	if (cpu_is_u5500())
		db5500_prcmu_early_init();
	if (cpu_is_u8500())
	if (cpu_is_u8500_family())
		db8500_prcmu_early_init();
	clk_init();
}
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