Commit bc71a20d authored by Eric Bernstein's avatar Eric Bernstein Committed by Alex Deucher
Browse files

drm/amd/display: Call ipp_program_bias_and_scale only if available 



Also move some register definitions to common DCN regs.

Signed-off-by: default avatarEric Bernstein <eric.bernstein@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f4dd6dca

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h

+8 −8
Original line number Diff line number Diff line
@@ -73,6 +73,9 @@ 
	SRI(RECOUT_START, DSCL, id), \

	SRI(RECOUT_SIZE, DSCL, id), \

	SRI(OBUF_CONTROL, DSCL, id), \

	SRI(CM_ICSC_CONTROL, CM, id), \

	SRI(CM_ICSC_C11_C12, CM, id), \

	SRI(CM_ICSC_C33_C34, CM, id), \

	SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \

	SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \

	SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
@@ -124,9 +127,6 @@ 
	SRI(CM_OCSC_CONTROL, CM, id), \

	SRI(CM_OCSC_C11_C12, CM, id), \

	SRI(CM_OCSC_C33_C34, CM, id), \

	SRI(CM_ICSC_CONTROL, CM, id), \

	SRI(CM_ICSC_C11_C12, CM, id), \

	SRI(CM_ICSC_C33_C34, CM, id), \

	SRI(CM_BNS_VALUES_R, CM, id), \

	SRI(CM_BNS_VALUES_G, CM, id), \

	SRI(CM_BNS_VALUES_B, CM, id), \
@@ -239,6 +239,11 @@ 
	TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\

	TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \

	TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \

	TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \

	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \

	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \

	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \

	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \

	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \

	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \

	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \
@@ -327,11 +332,6 @@ 
	TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \

	TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \

	TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \

	TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \

	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \

	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \

	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \

	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \

	TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \

	TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \

	TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+2 −1
Original line number Diff line number Diff line
@@ -1903,6 +1903,7 @@ static void update_dchubp_dpp( 


	//set scale and bias registers

	build_prescale_params(&bns_params, plane_state);

	if (dpp->funcs->ipp_program_bias_and_scale)

		dpp->funcs->ipp_program_bias_and_scale(dpp, &bns_params);



	mpcc_cfg.dpp_id = hubp->inst;

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