Commit bc6fe533 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2018-01-04' of... 

Merge tag 'drm-intel-fixes-2018-01-04' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes

drm/i915 fixes for v4.15-rc7
- couple of documentation build fixes
- serialize non-blocking modesets
- prevent DMC from messing up GMBUS transfers
- PSR regression fix

* tag 'drm-intel-fixes-2018-01-04' of git://anongit.freedesktop.org/drm/drm-intel:
  drm/i915: Apply Display WA #1183 on skl, kbl, and cfl
  docs: fix, intel_guc_loader.c has been moved to intel_guc_fw.c
  documentation/gpu/i915: fix docs build error after file rename
  drm/i915: Put all non-blocking modesets onto an ordered wq
  drm/i915: Disable DC states around GMBUS on GLK
  drm/i915/psr: Fix register name mess up.
parents 0007b9ca 30414f30

Documentation/gpu/i915.rst

+1 −4
Original line number Diff line number Diff line
@@ -341,10 +341,7 @@ GuC 
GuC-specific firmware loader

----------------------------



.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c

   :doc: GuC-specific firmware loader



.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c

.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c

   :internal:



GuC-based command submission

drivers/gpu/drm/i915/i915_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -2368,6 +2368,9 @@ struct drm_i915_private { 
	 */

	struct workqueue_struct *wq;



	/* ordered wq for modesets */

	struct workqueue_struct *modeset_wq;



	/* Display functions */

	struct drm_i915_display_funcs display;

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -6977,6 +6977,7 @@ enum { 
#define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)



#define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)

#define   SKL_SELECT_ALTERNATE_DC_EXIT	(1<<30)

#define   MASK_WAKEMEM			(1<<13)



#define SKL_DFSM			_MMIO(0x51000)
@@ -8522,6 +8523,7 @@ enum skl_power_gate { 
#define  BXT_CDCLK_CD2X_DIV_SEL_2	(2<<22)

#define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)

#define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe)<<20)

#define  CDCLK_DIVMUX_CD_OVERRIDE	(1<<19)

#define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)

#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)

#define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)

drivers/gpu/drm/i915/intel_cdclk.c

+26 −9
Original line number Diff line number Diff line
@@ -860,16 +860,10 @@ static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, 


static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)

{

	int min_cdclk = skl_calc_cdclk(0, vco);

	u32 val;



	WARN_ON(vco != 8100000 && vco != 8640000);



	/* select the minimum CDCLK before enabling DPLL 0 */

	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);

	I915_WRITE(CDCLK_CTL, val);

	POSTING_READ(CDCLK_CTL);



	/*

	 * We always enable DPLL0 with the lowest link rate possible, but still

	 * taking into account the VCO required to operate the eDP panel at the
@@ -923,7 +917,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, 
{

	int cdclk = cdclk_state->cdclk;

	int vco = cdclk_state->vco;

	u32 freq_select, pcu_ack;

	u32 freq_select, pcu_ack, cdclk_ctl;

	int ret;



	WARN_ON((cdclk == 24000) != (vco == 0));
@@ -940,7 +934,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, 
		return;

	}



	/* set CDCLK_CTL */

	/* Choose frequency for this cdclk */

	switch (cdclk) {

	case 450000:

	case 432000:
@@ -968,10 +962,33 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, 
	    dev_priv->cdclk.hw.vco != vco)

		skl_dpll0_disable(dev_priv);



	cdclk_ctl = I915_READ(CDCLK_CTL);



	if (dev_priv->cdclk.hw.vco != vco) {

		/* Wa Display #1183: skl,kbl,cfl */

		cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);

		cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);

		I915_WRITE(CDCLK_CTL, cdclk_ctl);

	}



	/* Wa Display #1183: skl,kbl,cfl */

	cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;

	I915_WRITE(CDCLK_CTL, cdclk_ctl);

	POSTING_READ(CDCLK_CTL);



	if (dev_priv->cdclk.hw.vco != vco)

		skl_dpll0_enable(dev_priv, vco);



	I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));

	/* Wa Display #1183: skl,kbl,cfl */

	cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);

	I915_WRITE(CDCLK_CTL, cdclk_ctl);



	cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);

	I915_WRITE(CDCLK_CTL, cdclk_ctl);



	/* Wa Display #1183: skl,kbl,cfl */

	cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;

	I915_WRITE(CDCLK_CTL, cdclk_ctl);

	POSTING_READ(CDCLK_CTL);



	/* inform PCU of the change */

drivers/gpu/drm/i915/intel_display.c

+11 −3
Original line number Diff line number Diff line
@@ -12544,11 +12544,15 @@ static int intel_atomic_commit(struct drm_device *dev, 
	INIT_WORK(&state->commit_work, intel_atomic_commit_work);



	i915_sw_fence_commit(&intel_state->commit_ready);

	if (nonblock)

	if (nonblock && intel_state->modeset) {

		queue_work(dev_priv->modeset_wq, &state->commit_work);

	} else if (nonblock) {

		queue_work(system_unbound_wq, &state->commit_work);

	else

	} else {

		if (intel_state->modeset)

			flush_workqueue(dev_priv->modeset_wq);

		intel_atomic_commit_tail(state);



	}



	return 0;

}
@@ -14462,6 +14466,8 @@ int intel_modeset_init(struct drm_device *dev) 
	enum pipe pipe;

	struct intel_crtc *crtc;



	dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);



	drm_mode_config_init(dev);



	dev->mode_config.min_width = 0;
@@ -15270,6 +15276,8 @@ void intel_modeset_cleanup(struct drm_device *dev) 
	intel_cleanup_gt_powersave(dev_priv);



	intel_teardown_gmbus(dev_priv);



	destroy_workqueue(dev_priv->modeset_wq);

}



void intel_connector_attach_encoder(struct intel_connector *connector,

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