Commit bc6e8dc1 authored by WANG Xuerui's avatar WANG Xuerui Committed by Thomas Bogendoerfer
Browse files

MIPS: handle Loongson-specific GSExc exception 



Newer Loongson cores (Loongson-3A R2 and newer) use the
implementation-dependent ExcCode 16 to signal Loongson-specific
exceptions. The extended cause is put in the non-standard CP0.Diag1
register which is CP0 Register 22 Select 1, called GSCause in Loongson
manuals. Inside is an exception code bitfield called GSExcCode, only
codes 0 to 6 inclusive are documented (so far, in the Loongson 3A3000
User Manual, Volume 2).

During experiments, it was found that some undocumented unprivileged
instructions can trigger the also-undocumented GSExcCode 8 on Loongson
3A4000. Processor state is not corrupted, but we cannot continue without
further knowledge, and Loongson is not providing that information as of
this writing. So we send SIGILL on seeing this exception code to thwart
easy local DoS attacks.

Other exception codes are made fatal, partly because of insufficient
knowledge, also partly because they are not as easily reproduced. None
of them are encountered in the wild with upstream kernels and userspace
so far.

Some older cores (Loongson-3A1000 and Loongson-3B1500) have ExcCode 16
too, but the semantic is equivalent to GSExcCode 0. Because the
respective manuals did not mention the CP0.Diag1 register or its read
behavior, these cores are not covered in this patch, as MFC0 from
non-existent CP0 registers is UNDEFINED according to the MIPS
architecture spec.

Reviewed-by: default avatarHuacai Chen <chenhc@lemote.com>
Signed-off-by: default avatarWANG Xuerui <git@xen0n.name>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 2480c914

arch/mips/include/asm/cpu-features.h

+4 −0
Original line number Diff line number Diff line
@@ -572,6 +572,10 @@ 
# define cpu_has_ftlbparex	__opt(MIPS_CPU_FTLBPAREX)

#endif



#ifndef cpu_has_gsexcex

# define cpu_has_gsexcex	__opt(MIPS_CPU_GSEXCEX)

#endif



#ifdef CONFIG_SMP

/*

 * Some systems share FTLB RAMs between threads within a core (siblings in

arch/mips/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -428,6 +428,7 @@ enum cpu_type_enum { 
#define MIPS_CPU_MM_FULL	BIT_ULL(59)	/* CPU supports write-through full merge */

#define MIPS_CPU_MAC_2008_ONLY	BIT_ULL(60)	/* CPU Only support MAC2008 Fused multiply-add instruction */

#define MIPS_CPU_FTLBPAREX	BIT_ULL(61)	/* CPU has FTLB parity exception */

#define MIPS_CPU_GSEXCEX	BIT_ULL(62)	/* CPU has GSExc exception */



/*

 * CPU ASE encodings

arch/mips/include/asm/mipsregs.h

+3 −0
Original line number Diff line number Diff line
@@ -474,6 +474,9 @@ 
/* Implementation specific trap codes used by MIPS cores */

#define MIPS_EXCCODE_TLBPAR	16	/* TLB parity error exception */



/* Implementation specific trap codes used by Loongson cores */

#define LOONGSON_EXCCODE_GSEXC	16	/* Loongson-specific exception */



/*

 * Bits in the coprocessor 0 config register.

 */

arch/mips/kernel/cpu-probe.c

+3 −0
Original line number Diff line number Diff line
@@ -2043,6 +2043,9 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 
{

	decode_configs(c);



	/* All Loongson processors covered here define ExcCode 16 as GSExc. */

	c->options |= MIPS_CPU_GSEXCEX;



	switch (c->processor_id & PRID_IMP_MASK) {

	case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */

		switch (c->processor_id & PRID_REV_MASK) {

arch/mips/kernel/genex.S

+14 −0
Original line number Diff line number Diff line
@@ -498,6 +498,19 @@ NESTED(nmi_handler, PT_SIZE, sp) 
	KMODE

	.endm



	.macro __build_clear_gsexc

	.set	push

	/*

	 * We need to specify a selector to access the CP0.Diag1 (GSCause)

	 * register. All GSExc-equipped processors have MIPS32.

	 */

	.set	mips32

	mfc0	a1, CP0_DIAGNOSTIC1

	.set	pop

	TRACE_IRQS_ON

	STI

	.endm



	.macro	__BUILD_silent exception

	.endm
@@ -556,6 +569,7 @@ NESTED(nmi_handler, PT_SIZE, sp) 
	BUILD_HANDLER fpe fpe fpe silent		/* #15 */

#endif

	BUILD_HANDLER ftlb ftlb none silent		/* #16 */

	BUILD_HANDLER gsexc gsexc gsexc silent		/* #16 */

	BUILD_HANDLER msa msa sti silent		/* #21 */

	BUILD_HANDLER mdmx mdmx sti silent		/* #22 */

#ifdef	CONFIG_HARDWARE_WATCHPOINTS

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