Commit bc66392d authored by Stoica Cosmin-Stefan's avatar Stoica Cosmin-Stefan Committed by Shawn Guo
Browse files

arm64: dts: fsl: Add device tree for S32V234-EVB 



Add initial version of device tree for S32V234-EVB, including nodes for the
4 Cortex-A53 cores, AIPS bus with UART modules, ARM architected timer and
Generic Interrupt Controller (GIC).

Keep SoC level separate from board level to let future boards with this SoC
share common properties, while the dts files will keep board-dependent
properties.

Signed-off-by: default avatarStoica Cosmin-Stefan <cosmin.stoica@nxp.com>
Signed-off-by: default avatarMihaela Martinas <Mihaela.Martinas@freescale.com>
Signed-off-by: default avatarDan Nica <dan.nica@nxp.com>
Signed-off-by: default avatarLarisa Grigore <Larisa.Grigore@nxp.com>
Signed-off-by: default avatarPhu Luu An <phu.luuan@nxp.com>
Signed-off-by: default avatarStefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent e8b395b2

arch/arm64/boot/dts/freescale/Makefile

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Original line number Diff line number Diff line
@@ -32,3 +32,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb 
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb



dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb

arch/arm64/boot/dts/freescale/s32v234-evb.dts

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+25 −0
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// SPDX-License-Identifier: GPL-2.0-or-later

/*

 * Copyright 2015-2016 Freescale Semiconductor, Inc.

 * Copyright 2016-2017 NXP

 */



/dts-v1/;

#include "s32v234.dtsi"



/ {

	model = "NXP S32V234-EVB2 Board";

	compatible = "fsl,s32v234-evb", "fsl,s32v234";



	chosen {

		stdout-path = "serial0:115200n8";

	};

};



&uart0 {

	status = "okay";

};



&uart1 {

	status = "okay";

};

arch/arm64/boot/dts/freescale/s32v234.dtsi

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+139 −0
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// SPDX-License-Identifier: GPL-2.0-or-later

/*

 * Copyright 2015-2016 Freescale Semiconductor, Inc.

 * Copyright 2016-2018 NXP

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>



/memreserve/ 0x80000000 0x00010000;



/ {

	compatible = "fsl,s32v234";

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	aliases {

		serial0 = &uart0;

		serial1 = &uart1;

	};



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x0>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x80000000>;

			next-level-cache = <&cluster0_l2_cache>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x1>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x80000000>;

			next-level-cache = <&cluster0_l2_cache>;

		};



		cpu2: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x100>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x80000000>;

			next-level-cache = <&cluster1_l2_cache>;

		};



		cpu3: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x101>;

			enable-method = "spin-table";

			cpu-release-addr = <0x0 0x80000000>;

			next-level-cache = <&cluster1_l2_cache>;

		};



		cluster0_l2_cache: l2-cache0 {

			compatible = "cache";

		};



		cluster1_l2_cache: l2-cache1 {

			compatible = "cache";

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |

					  IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |

					  IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |

					  IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |

					  IRQ_TYPE_LEVEL_LOW)>;

		/* clock-frequency might be modified by u-boot, depending on the

		 * chip version.

		 */

		clock-frequency = <10000000>;

	};



	gic: interrupt-controller@7d001000 {

		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";

		#interrupt-cells = <3>;

		#address-cells = <0>;

		interrupt-controller;

		reg = <0 0x7d001000 0 0x1000>,

		      <0 0x7d002000 0 0x2000>,

		      <0 0x7d004000 0 0x2000>,

		      <0 0x7d006000 0 0x2000>;

		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |

					 IRQ_TYPE_LEVEL_HIGH)>;

	};



	soc {

		#address-cells = <2>;

		#size-cells = <2>;

		compatible = "simple-bus";

		interrupt-parent = <&gic>;

		ranges;



		aips0: aips-bus@40000000 {

			compatible = "simple-bus";

			#address-cells = <2>;

			#size-cells = <2>;

			interrupt-parent = <&gic>;

			reg = <0x0 0x40000000 0x0 0x7d000>;

			ranges;



			uart0: serial@40053000 {

				compatible = "fsl,s32v234-linflexuart";

				reg = <0x0 0x40053000 0x0 0x1000>;

				interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;

				status = "disabled";

			};

		};



		aips1: aips-bus@40080000 {

			compatible = "simple-bus";

			#address-cells = <2>;

			#size-cells = <2>;

			interrupt-parent = <&gic>;

			reg = <0x0 0x40080000 0x0 0x70000>;

			ranges;



			uart1: serial@400bc000 {

				compatible = "fsl,s32v234-linflexuart";

				reg = <0x0 0x400bc000 0x0 0x1000>;

				interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;

				status = "disabled";

			};

		};

	};

};

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