Commit bc580b56 authored by Vivek Gautam's avatar Vivek Gautam Committed by Will Deacon
Browse files

iommu/arm-smmu: Log CBFRSYNRA register on context fault 



Bits[15:0] in CBFRSYNRA register contain information about
StreamID of the incoming transaction that generated the
fault. Dump CBFRSYNRA register to get this info.
This is specially useful in a distributed SMMU architecture
where multiple masters are connected to the SMMU.
SID information helps to quickly identify the faulting
master device.

Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: default avatarRobin Murphy <robin.murphy@arm.com>
Acked-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: default avatarVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 3f54c447

drivers/iommu/arm-smmu-regs.h

+2 −0
Original line number Diff line number Diff line
@@ -147,6 +147,8 @@ enum arm_smmu_s2cr_privcfg { 
#define CBAR_IRPTNDX_SHIFT		24

#define CBAR_IRPTNDX_MASK		0xff



#define ARM_SMMU_GR1_CBFRSYNRA(n)	(0x400 + ((n) << 2))



#define ARM_SMMU_GR1_CBA2R(n)		(0x800 + ((n) << 2))

#define CBA2R_RW64_32BIT		(0 << 0)

#define CBA2R_RW64_64BIT		(1 << 0)

drivers/iommu/arm-smmu.c

+5 −3
Original line number Diff line number Diff line
@@ -570,12 +570,13 @@ static const struct iommu_gather_ops arm_smmu_s2_tlb_ops_v1 = { 


static irqreturn_t arm_smmu_context_fault(int irq, void *dev)

{

	u32 fsr, fsynr;

	u32 fsr, fsynr, cbfrsynra;

	unsigned long iova;

	struct iommu_domain *domain = dev;

	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);

	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;

	struct arm_smmu_device *smmu = smmu_domain->smmu;

	void __iomem *gr1_base = ARM_SMMU_GR1(smmu);

	void __iomem *cb_base;



	cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);
@@ -586,10 +587,11 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) 


	fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);

	iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);

	cbfrsynra = readl_relaxed(gr1_base + ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));



	dev_err_ratelimited(smmu->dev,

	"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cb=%d\n",

			    fsr, iova, fsynr, cfg->cbndx);

	"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",

			    fsr, iova, fsynr, cbfrsynra, cfg->cbndx);



	writel(fsr, cb_base + ARM_SMMU_CB_FSR);

	return IRQ_HANDLED;

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