Commit bc41b872 authored Sep 27, 2013 by Santosh Shilimkar Committed by Russell King Oct 03, 2013

ARM: 7846/1: Update SMP_ON_UP code to detect A9MPCore with 1 CPU devices



The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP core IP with 1 CPU as configuration. To let
these SOCs to co-exist in a CONFIG_SMP=y build by leveraging
the SMP_ON_UP support, we need to additionally check the
number the cores in Cortex-A9 MPCore configuration. Without
such a check in place, the startup code tries to execute
ALT_SMP() set of instructions which lead to CPU faults.

The issue was spotted on TI's Aegis device and this patch
makes now the device work with omap2plus_defconfig which
enables SMP by default. The change is kept limited to only
Cortex-A9 MPCore detection code.

Note that if any future SoC *does* use 0x0 as the PERIPH_BASE, then
the SCU address check code needs to be #ifdef'd for for the Aegis
platform.

Acked-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

parent 85633728

arch/arm/kernel/head.S

+20 −1

Original line number	Diff line number	Diff line
		@@ -487,7 +487,26 @@ __fixup_smp:
		mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
		and r0, r0, #0xc0000000 @ multiprocessing extensions and
		teq r0, #0x80000000 @ not part of a uniprocessor system?
		moveq pc, lr @ yes, assume SMP
		bne __fixup_smp_on_up @ no, assume UP

		@ Core indicates it is SMP. Check for Aegis SOC where a single
		@ Cortex-A9 CPU is present but SMP operations fault.
		mov r4, #0x41000000
		orr r4, r4, #0x0000c000
		orr r4, r4, #0x00000090
		teq r3, r4 @ Check for ARM Cortex-A9
		movne pc, lr @ Not ARM Cortex-A9,

		@ If a future SoC does use 0x0 as the PERIPH_BASE, then the
		@ below address check will need to be #ifdef'd or equivalent
		@ for the Aegis platform.
		mrc p15, 4, r0, c15, c0 @ get SCU base address
		teq r0, #0x0 @ '0' on actual UP A9 hardware
		beq __fixup_smp_on_up @ So its an A9 UP
		ldr r0, [r0, #4] @ read SCU Config
		and r0, r0, #0x3 @ number of CPUs
		teq r0, #0x0 @ is 1?
		movne pc, lr

		__fixup_smp_on_up:
		adr r0, 1f

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