Commit bc3ec75d authored by Christoph Hellwig's avatar Christoph Hellwig
Browse files

dma-mapping: merge direct and noncoherent ops 



All the cache maintainance is already stubbed out when not enabled,
but merging the two allows us to nicely handle the case where
cache maintainance is required for some devices, but not others.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Acked-by: Paul Burton <paul.burton@mips.com> # MIPS parts
parent f3ecc0ff

arch/arc/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ config ARC 
	select BUILDTIME_EXTABLE_SORT

	select CLONE_BACKWARDS

	select COMMON_CLK

	select DMA_NONCOHERENT_OPS

	select DMA_DIRECT_OPS

	select DMA_NONCOHERENT_MMAP

	select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)

	select GENERIC_CLOCKEVENTS

arch/arc/mm/dma.c

+7 −9
Original line number Diff line number Diff line
@@ -167,7 +167,7 @@ void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr, 
}



/*

 * Plug in coherent or noncoherent dma ops

 * Plug in direct dma map ops.

 */

void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,

			const struct iommu_ops *iommu, bool coherent)
@@ -175,13 +175,11 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, 
	/*

	 * IOC hardware snoops all DMA traffic keeping the caches consistent

	 * with memory - eliding need for any explicit cache maintenance of

	 * DMA buffers - so we can use dma_direct cache ops.

	 * DMA buffers.

	 */

	if (is_isa_arcv2() && ioc_enable && coherent) {

		set_dma_ops(dev, &dma_direct_ops);

		dev_info(dev, "use dma_direct_ops cache ops\n");

	} else {

		set_dma_ops(dev, &dma_noncoherent_ops);

		dev_info(dev, "use dma_noncoherent_ops cache ops\n");

	}

	if (is_isa_arcv2() && ioc_enable && coherent)

		dev->dma_coherent = true;



	dev_info(dev, "use %sncoherent DMA ops\n",

		 dev->dma_coherent ? "" : "non");

}

arch/arm/mm/dma-mapping-nommu.c

+3 −2
Original line number Diff line number Diff line
@@ -47,7 +47,8 @@ static void *arm_nommu_dma_alloc(struct device *dev, size_t size, 
	 */



	if (attrs & DMA_ATTR_NON_CONSISTENT)

		return dma_direct_alloc(dev, size, dma_handle, gfp, attrs);

		return dma_direct_alloc_pages(dev, size, dma_handle, gfp,

				attrs);



	ret = dma_alloc_from_global_coherent(size, dma_handle);
@@ -70,7 +71,7 @@ static void arm_nommu_dma_free(struct device *dev, size_t size, 
			       unsigned long attrs)

{

	if (attrs & DMA_ATTR_NON_CONSISTENT) {

		dma_direct_free(dev, size, cpu_addr, dma_addr, attrs);

		dma_direct_free_pages(dev, size, cpu_addr, dma_addr, attrs);

	} else {

		int ret = dma_release_from_global_coherent(get_order(size),

							   cpu_addr);

arch/c6x/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ config C6X 
	select ARCH_HAS_SYNC_DMA_FOR_CPU

	select ARCH_HAS_SYNC_DMA_FOR_DEVICE

	select CLKDEV_LOOKUP

	select DMA_NONCOHERENT_OPS

	select DMA_DIRECT_OPS

	select GENERIC_ATOMIC64

	select GENERIC_IRQ_SHOW

	select HAVE_ARCH_TRACEHOOK

arch/hexagon/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ config HEXAGON 
	select GENERIC_CLOCKEVENTS_BROADCAST

	select MODULES_USE_ELF_RELA

	select GENERIC_CPU_DEVICES

	select DMA_NONCOHERENT_OPS

	select DMA_DIRECT_OPS

	---help---

	  Qualcomm Hexagon is a processor architecture designed for high

	  performance and low power across a wide variety of applications.

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