Unverified Commit bc3d9243 authored by Mark Brown's avatar Mark Brown
Browse files

Merge series "spi: Fixes for FSI-attached controller" from Eddie James <eajames@linux.ibm.com>: 

This series implements a number of fixes for the FSI-attached SPI
controller driver.

Changes since v1:
 - Switch to a new compatible string for the restricted version of the
   SPI controller, rather than a new boolean parameter.

Brad Bishop (3):
  spi: fsi: Handle 9 to 15 byte transfers lengths
  spi: fsi: Fix clock running too fast
  spi: fsi: Fix use of the bneq+ sequencer instruction

Eddie James (3):
  dt-bindings: fsi: fsi2spi: Add compatible string for restricted
    version
  spi: fsi: Implement restricted size for certain controllers
  spi: fsi: Check mux status before transfers

 .../devicetree/bindings/fsi/ibm,fsi2spi.yaml  |   1 +
 drivers/spi/spi-fsi.c                         | 139 ++++++++++++++----
 2 files changed, 109 insertions(+), 31 deletions(-)

--
2.26.2
parents 9599f341 b0e4dfe9

Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ properties: 
  compatible:

    enum:

      - ibm,fsi2spi

      - ibm,fsi2spi-restricted



  reg:

    items:

drivers/spi/spi-fsi.c

+108 −31
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 


#define FSI_ENGID_SPI			0x23

#define FSI_MBOX_ROOT_CTRL_8		0x2860

#define  FSI_MBOX_ROOT_CTRL_8_SPI_MUX	 0xf0000000



#define FSI2SPI_DATA0			0x00

#define FSI2SPI_DATA1			0x04
@@ -24,11 +25,16 @@ 


#define SPI_FSI_BASE			0x70000

#define SPI_FSI_INIT_TIMEOUT_MS		1000

#define SPI_FSI_MAX_TRANSFER_SIZE	2048

#define SPI_FSI_MAX_XFR_SIZE		2048

#define SPI_FSI_MAX_XFR_SIZE_RESTRICTED	32



#define SPI_FSI_ERROR			0x0

#define SPI_FSI_COUNTER_CFG		0x1

#define  SPI_FSI_COUNTER_CFG_LOOPS(x)	 (((u64)(x) & 0xffULL) << 32)

#define  SPI_FSI_COUNTER_CFG_N2_RX	 BIT_ULL(8)

#define  SPI_FSI_COUNTER_CFG_N2_TX	 BIT_ULL(9)

#define  SPI_FSI_COUNTER_CFG_N2_IMPLICIT BIT_ULL(10)

#define  SPI_FSI_COUNTER_CFG_N2_RELOAD	 BIT_ULL(11)

#define SPI_FSI_CFG1			0x2

#define SPI_FSI_CLOCK_CFG		0x3

#define  SPI_FSI_CLOCK_CFG_MM_ENABLE	 BIT_ULL(32)
@@ -61,7 +67,7 @@ 
#define  SPI_FSI_STATUS_RDR_OVERRUN	 BIT_ULL(62)

#define  SPI_FSI_STATUS_RDR_FULL	 BIT_ULL(63)

#define  SPI_FSI_STATUS_ANY_ERROR	 \

	(SPI_FSI_STATUS_ERROR | SPI_FSI_STATUS_TDR_UNDERRUN | \

	(SPI_FSI_STATUS_ERROR | \

	 SPI_FSI_STATUS_TDR_OVERRUN | SPI_FSI_STATUS_RDR_UNDERRUN | \

	 SPI_FSI_STATUS_RDR_OVERRUN)

#define SPI_FSI_PORT_CTRL		0x9
@@ -70,6 +76,8 @@ struct fsi_spi { 
	struct device *dev;	/* SPI controller device */

	struct fsi_device *fsi;	/* FSI2SPI CFAM engine device */

	u32 base;

	size_t max_xfr_size;

	bool restricted;

};



struct fsi_spi_sequence {
@@ -77,6 +85,26 @@ struct fsi_spi_sequence { 
	u64 data;

};



static int fsi_spi_check_mux(struct fsi_device *fsi, struct device *dev)

{

	int rc;

	u32 root_ctrl_8;

	__be32 root_ctrl_8_be;



	rc = fsi_slave_read(fsi->slave, FSI_MBOX_ROOT_CTRL_8, &root_ctrl_8_be,

			    sizeof(root_ctrl_8_be));

	if (rc)

		return rc;



	root_ctrl_8 = be32_to_cpu(root_ctrl_8_be);

	dev_dbg(dev, "Root control register 8: %08x\n", root_ctrl_8);

	if ((root_ctrl_8 & FSI_MBOX_ROOT_CTRL_8_SPI_MUX) ==

	     FSI_MBOX_ROOT_CTRL_8_SPI_MUX)

		return 0;



	return -ENOLINK;

}



static int fsi_spi_check_status(struct fsi_spi *ctx)

{

	int rc;
@@ -205,8 +233,12 @@ static int fsi_spi_reset(struct fsi_spi *ctx) 
	if (rc)

		return rc;



	return fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,

	rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,

			       SPI_FSI_CLOCK_CFG_RESET2);

	if (rc)

		return rc;



	return fsi_spi_write_reg(ctx, SPI_FSI_STATUS, 0ULL);

}



static int fsi_spi_sequence_add(struct fsi_spi_sequence *seq, u8 val)
@@ -214,8 +246,8 @@ static int fsi_spi_sequence_add(struct fsi_spi_sequence *seq, u8 val) 
	/*

	 * Add the next byte of instruction to the 8-byte sequence register.

	 * Then decrement the counter so that the next instruction will go in

	 * the right place. Return the number of "slots" left in the sequence

	 * register.

	 * the right place. Return the index of the slot we just filled in the

	 * sequence register.

	 */

	seq->data |= (u64)val << seq->bit;

	seq->bit -= 8;
@@ -233,40 +265,71 @@ static int fsi_spi_sequence_transfer(struct fsi_spi *ctx, 
				     struct fsi_spi_sequence *seq,

				     struct spi_transfer *transfer)

{

	bool docfg = false;

	int loops;

	int idx;

	int rc;

	u8 val = 0;

	u8 len = min(transfer->len, 8U);

	u8 rem = transfer->len % len;

	u64 cfg = 0ULL;



	loops = transfer->len / len;



	if (transfer->tx_buf) {

		idx = fsi_spi_sequence_add(seq,

					   SPI_FSI_SEQUENCE_SHIFT_OUT(len));

		val = SPI_FSI_SEQUENCE_SHIFT_OUT(len);

		idx = fsi_spi_sequence_add(seq, val);



		if (rem)

			rem = SPI_FSI_SEQUENCE_SHIFT_OUT(rem);

	} else if (transfer->rx_buf) {

		idx = fsi_spi_sequence_add(seq,

					   SPI_FSI_SEQUENCE_SHIFT_IN(len));

		val = SPI_FSI_SEQUENCE_SHIFT_IN(len);

		idx = fsi_spi_sequence_add(seq, val);



		if (rem)

			rem = SPI_FSI_SEQUENCE_SHIFT_IN(rem);

	} else {

		return -EINVAL;

	}



	if (ctx->restricted) {

		const int eidx = rem ? 5 : 6;



		while (loops > 1 && idx <= eidx) {

			idx = fsi_spi_sequence_add(seq, val);

			loops--;

			docfg = true;

		}



		if (loops > 1) {

			dev_warn(ctx->dev, "No sequencer slots; aborting.\n");

			return -EINVAL;

		}

	}



	if (loops > 1) {

		fsi_spi_sequence_add(seq, SPI_FSI_SEQUENCE_BRANCH(idx));

		docfg = true;

	}



		if (rem)

			fsi_spi_sequence_add(seq, rem);

	if (docfg) {

		cfg = SPI_FSI_COUNTER_CFG_LOOPS(loops - 1);

		if (transfer->rx_buf)

			cfg |= SPI_FSI_COUNTER_CFG_N2_RX |

				SPI_FSI_COUNTER_CFG_N2_TX |

				SPI_FSI_COUNTER_CFG_N2_IMPLICIT |

				SPI_FSI_COUNTER_CFG_N2_RELOAD;



		rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG,

				       SPI_FSI_COUNTER_CFG_LOOPS(loops - 1));

		rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, cfg);

		if (rc)

			return rc;

	} else {

		fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL);

	}



	if (rem)

		fsi_spi_sequence_add(seq, rem);



	return 0;

}
@@ -275,6 +338,7 @@ static int fsi_spi_transfer_data(struct fsi_spi *ctx, 
{

	int rc = 0;

	u64 status = 0ULL;

	u64 cfg = 0ULL;



	if (transfer->tx_buf) {

		int nb;
@@ -312,6 +376,16 @@ static int fsi_spi_transfer_data(struct fsi_spi *ctx, 
		u64 in = 0ULL;

		u8 *rx = transfer->rx_buf;



		rc = fsi_spi_read_reg(ctx, SPI_FSI_COUNTER_CFG, &cfg);

		if (rc)

			return rc;



		if (cfg & SPI_FSI_COUNTER_CFG_N2_IMPLICIT) {

			rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, 0);

			if (rc)

				return rc;

		}



		while (transfer->len > recv) {

			do {

				rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS,
@@ -350,7 +424,7 @@ static int fsi_spi_transfer_init(struct fsi_spi *ctx) 
	u64 status = 0ULL;

	u64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE |

		SPI_FSI_CLOCK_CFG_SCK_NO_DEL |

		FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 4);

		FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 19);



	end = jiffies + msecs_to_jiffies(SPI_FSI_INIT_TIMEOUT_MS);

	do {
@@ -396,18 +470,22 @@ static int fsi_spi_transfer_init(struct fsi_spi *ctx) 
static int fsi_spi_transfer_one_message(struct spi_controller *ctlr,

					struct spi_message *mesg)

{

	int rc = 0;

	int rc;

	u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(mesg->spi->chip_select + 1);

	struct spi_transfer *transfer;

	struct fsi_spi *ctx = spi_controller_get_devdata(ctlr);



	rc = fsi_spi_check_mux(ctx->fsi, ctx->dev);

	if (rc)

		return rc;



	list_for_each_entry(transfer, &mesg->transfers, transfer_list) {

		struct fsi_spi_sequence seq;

		struct spi_transfer *next = NULL;



		/* Sequencer must do shift out (tx) first. */

		if (!transfer->tx_buf ||

		    transfer->len > SPI_FSI_MAX_TRANSFER_SIZE) {

		    transfer->len > (ctx->max_xfr_size + 8)) {

			rc = -EINVAL;

			goto error;

		}
@@ -431,7 +509,7 @@ static int fsi_spi_transfer_one_message(struct spi_controller *ctlr, 


			/* Sequencer can only do shift in (rx) after tx. */

			if (next->rx_buf) {

				if (next->len > SPI_FSI_MAX_TRANSFER_SIZE) {

				if (next->len > ctx->max_xfr_size) {

					rc = -EINVAL;

					goto error;

				}
@@ -476,30 +554,21 @@ error: 


static size_t fsi_spi_max_transfer_size(struct spi_device *spi)

{

	return SPI_FSI_MAX_TRANSFER_SIZE;

	struct fsi_spi *ctx = spi_controller_get_devdata(spi->controller);



	return ctx->max_xfr_size;

}



static int fsi_spi_probe(struct device *dev)

{

	int rc;

	u32 root_ctrl_8;

	struct device_node *np;

	int num_controllers_registered = 0;

	struct fsi_device *fsi = to_fsi_dev(dev);



	/*

	 * Check the SPI mux before attempting to probe. If the mux isn't set

	 * then the SPI controllers can't access their slave devices.

	 */

	rc = fsi_slave_read(fsi->slave, FSI_MBOX_ROOT_CTRL_8, &root_ctrl_8,

			    sizeof(root_ctrl_8));

	rc = fsi_spi_check_mux(fsi, dev);

	if (rc)

		return rc;



	if (!root_ctrl_8) {

		dev_dbg(dev, "SPI mux not set, aborting probe.\n");

		return -ENODEV;

	}



	for_each_available_child_of_node(dev->of_node, np) {

		u32 base;
@@ -524,6 +593,14 @@ static int fsi_spi_probe(struct device *dev) 
		ctx->fsi = fsi;

		ctx->base = base + SPI_FSI_BASE;



		if (of_device_is_compatible(np, "ibm,fsi2spi-restricted")) {

			ctx->restricted = true;

			ctx->max_xfr_size = SPI_FSI_MAX_XFR_SIZE_RESTRICTED;

		} else {

			ctx->restricted = false;

			ctx->max_xfr_size = SPI_FSI_MAX_XFR_SIZE;

		}



		rc = devm_spi_register_controller(dev, ctlr);

		if (rc)

			spi_controller_put(ctlr);

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