Commit bc3b3f4b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.7 kernel cycle.

  There are no core changes this time, only driver developments:

   - New driver for the Dialog Semiconductor DA9062 Power Management
     Integrated Circuit (PMIC).

   - Renesas SH-PFC has improved consistency, with group and register
     checks in the configuration checker.

   - New subdriver for the Qualcomm IPQ6018.

   - Add the RGMII pin control functionality to Qualcomm IPQ8064.

   - Performance and code quality cleanups in the Mediatek driver.

   - Improve the Broadcom BCM2835 support to cover all the GPIOs that
     exist in it.

   - The Allwinner/Sunxi driver properly masks non-wakeup IRQs on
     suspend.

   - Add some missing groups and functions to the Ingenic driver.

   - Convert some of the Freescale device tree bindings to use the new
     and all improved JSON YAML markup.

   - Refactorings and support for the SFIO/GPIO in the Tegra194 SoC
     driver.

   - Support high impedance mode in the Spreadtrum/Unisoc driver"

* tag 'pinctrl-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (64 commits)
  pinctrl: qcom: fix compilation error
  pinctrl: qcom: use scm_call to route GPIO irq to Apps
  pinctrl: sprd: Add pin high impedance mode support
  pinctrl: sprd: Use the correct pin output configuration
  pinctrl: tegra: Add SFIO/GPIO programming on Tegra194
  pinctrl: tegra: Renumber the GG.0 and GG.1 pins
  pinctrl: tegra: Do not add default pin range on Tegra194
  pinctrl: tegra: Pass struct tegra_pmx for pin range check
  pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo
  pinctrl: tegra: Fix whitespace issues for improved readability
  pinctrl: mediatek: Use scnprintf() for avoiding potential buffer overflow
  pinctrl: freescale: drop the dependency on ARM64 for i.MX8M
  Revert "pinctrl: mvebu: armada-37xx: use use platform api"
  dt-bindings: pinctrl: at91: Fix a typo ("descibe")
  pinctrl: meson: add tsin pinctrl for meson gxbb/gxl/gxm
  pinctrl: sprd: Fix the kconfig warning
  pinctrl: ingenic: add hdmi-ddc pin control group
  pinctrl: sirf/atlas7: Replace zero-length array with flexible-array member
  pinctrl: sprd: Allow the SPRD pinctrl driver building into a module
  pinctrl: Export some needed symbols at module load time
  ...
parents 11786191 c42f69b4

Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt

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Original line number Diff line number Diff line
@@ -38,7 +38,7 @@ Bank: 3 (A, B and C) 
  0xffffffff 0x7fff3ccf  /* pioB */

  0xffffffff 0x007fffff  /* pioC */



For each peripheral/bank we will descibe in a u32 if a pin can be

For each peripheral/bank we will describe in a u32 if a pin can be

configured in it by putting 1 to the pin bit (1 << pin)



Let's take the pioA on peripheral B

Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.txt

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* Freescale IMX8MM IOMUX Controller



Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory

for common binding part and usage.



Required properties:

- compatible: "fsl,imx8mm-iomuxc"

- reg: should contain the base physical address and size of the iomuxc

  registers.



Required properties in sub-nodes:

- fsl,pins: each entry consists of 6 integers and represents the mux and config

  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val

  input_val> are specified using a PIN_FUNC_ID macro, which can be found in

  <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last integer CONFIG is

  the pad setting value like pull-up on this pin.  Please refer to i.MX8M Mini

  Reference Manual for detailed CONFIG settings.



Examples:



&uart1 {

       pinctrl-names = "default";

       pinctrl-0 = <&pinctrl_uart1>;

};



iomuxc: pinctrl@30330000 {

        compatible = "fsl,imx8mm-iomuxc";

        reg = <0x0 0x30330000 0x0 0x10000>;



        pinctrl_uart1: uart1grp {

                fsl,pins = <

                        MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX             0x140

                        MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX             0x140

                >;

        };

};

Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mm-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale IMX8MM IOMUX Controller



maintainers:

  - Anson Huang <Anson.Huang@nxp.com>



description:

  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory

  for common binding part and usage.



properties:

  compatible:

    const: fsl,imx8mm-iomuxc



  reg:

    maxItems: 1



# Client device subnode's properties

patternProperties:

  'grp$':

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.



    properties:

      fsl,pins:

        description:

          each entry consists of 6 integers and represents the mux and config

          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg

          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can

          be found in <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last

          integer CONFIG is the pad setting value like pull-up on this pin. Please

          refer to i.MX8M Mini Reference Manual for detailed CONFIG settings.

        allOf:

          - $ref: /schemas/types.yaml#/definitions/uint32-matrix

          - items:

              items:

                - description: |

                    "mux_reg" indicates the offset of mux register.

                - description: |

                    "conf_reg" indicates the offset of pad configuration register.

                - description: |

                    "input_reg" indicates the offset of select input register.

                - description: |

                    "mux_val" indicates the mux value to be applied.

                - description: |

                    "input_val" indicates the select input value to be applied.

                - description: |

                    "pad_setting" indicates the pad configuration value to be applied.



    required:

      - fsl,pins



    additionalProperties: false



required:

  - compatible

  - reg



additionalProperties: false



examples:

  # Pinmux controller node

  - |

    iomuxc: pinctrl@30330000 {

        compatible = "fsl,imx8mm-iomuxc";

        reg = <0x30330000 0x10000>;



        pinctrl_uart2: uart2grp {

            fsl,pins =

                <0x23C 0x4A4 0x4FC 0x0 0x0	0x140>,

                <0x240 0x4A8 0x000 0x0 0x0	0x140>;

        };

    };



...

Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.txt

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* Freescale IMX8MN IOMUX Controller



Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory

for common binding part and usage.



Required properties:

- compatible: "fsl,imx8mn-iomuxc"

- reg: should contain the base physical address and size of the iomuxc

  registers.



Required properties in sub-nodes:

- fsl,pins: each entry consists of 6 integers and represents the mux and config

  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val

  input_val> are specified using a PIN_FUNC_ID macro, which can be found in

  <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last integer CONFIG is

  the pad setting value like pull-up on this pin. Please refer to i.MX8M Nano

  Reference Manual for detailed CONFIG settings.



Examples:



&uart1 {

       pinctrl-names = "default";

       pinctrl-0 = <&pinctrl_uart1>;

};



iomuxc: pinctrl@30330000 {

        compatible = "fsl,imx8mn-iomuxc";

        reg = <0x0 0x30330000 0x0 0x10000>;



        pinctrl_uart1: uart1grp {

                fsl,pins = <

			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140

			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140

			MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140

			MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140

			MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6	0x19

                >;

        };

};

Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mn-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale IMX8MN IOMUX Controller



maintainers:

  - Anson Huang <Anson.Huang@nxp.com>



description:

  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory

  for common binding part and usage.



properties:

  compatible:

    const: fsl,imx8mn-iomuxc



  reg:

    maxItems: 1



# Client device subnode's properties

patternProperties:

  'grp$':

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.



    properties:

      fsl,pins:

        description:

          each entry consists of 6 integers and represents the mux and config

          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg

          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can

          be found in <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last

          integer CONFIG is the pad setting value like pull-up on this pin. Please

          refer to i.MX8M Nano Reference Manual for detailed CONFIG settings.

        allOf:

          - $ref: /schemas/types.yaml#/definitions/uint32-matrix

          - items:

              items:

                - description: |

                    "mux_reg" indicates the offset of mux register.

                - description: |

                    "conf_reg" indicates the offset of pad configuration register.

                - description: |

                    "input_reg" indicates the offset of select input register.

                - description: |

                    "mux_val" indicates the mux value to be applied.

                - description: |

                    "input_val" indicates the select input value to be applied.

                - description: |

                    "pad_setting" indicates the pad configuration value to be applied.



    required:

      - fsl,pins



    additionalProperties: false



required:

  - compatible

  - reg



additionalProperties: false



examples:

  # Pinmux controller node

  - |

    iomuxc: pinctrl@30330000 {

        compatible = "fsl,imx8mn-iomuxc";

        reg = <0x30330000 0x10000>;



        pinctrl_uart2: uart2grp {

            fsl,pins =

                <0x23C 0x4A4 0x4FC 0x0 0x0	0x140>,

                <0x240 0x4A8 0x000 0x0 0x0	0x140>;

        };

    };



...

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