Merge branch 'for-next/rng' into for-next/core (bc206065) · Commits · 戴 / test

Documentation/arm64/cpu-feature-registers.rst

+2 −0

Original line number	Diff line number	Diff line
		@@ -117,6 +117,8 @@ infrastructure:
		+------------------------------+---------+---------+
		\| Name \| bits \| visible \|
		+------------------------------+---------+---------+
		\| RNDR \| [63-60] \| y \|
		+------------------------------+---------+---------+
		\| TS \| [55-52] \| y \|
		+------------------------------+---------+---------+
		\| FHM \| [51-48] \| y \|

Documentation/arm64/elf_hwcaps.rst

+4 −0

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		@@ -232,6 +232,10 @@ HWCAP2_DGH

		Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001.

		HWCAP2_RNG

		Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001.

		4. Unused AT_HWCAP bits
		-----------------------

arch/arm64/Kconfig

+8 −0

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		@@ -1528,6 +1528,14 @@ config ARM64_E0PD

		This option enables E0PD for TTBR1 where available.

		config ARCH_RANDOM
		bool "Enable support for random number generation"
		default y
		help
		Random number generation (part of the ARMv8.5 Extensions)
		provides a high bandwidth, cryptographically secure
		hardware random number generator.

		endmenu

		config ARM64_SVE

arch/arm64/include/asm/archrandom.h

0 → 100644

+75 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0 */
		#ifndef _ASM_ARCHRANDOM_H
		#define _ASM_ARCHRANDOM_H

		#ifdef CONFIG_ARCH_RANDOM

		#include <linux/random.h>
		#include <asm/cpufeature.h>

		static inline bool __arm64_rndr(unsigned long *v)
		{
		bool ok;

		/*
		* Reads of RNDR set PSTATE.NZCV to 0b0000 on success,
		* and set PSTATE.NZCV to 0b0100 otherwise.
		*/
		asm volatile(
		__mrs_s("%0", SYS_RNDR_EL0) "\n"
		" cset %w1, ne\n"
		: "=r" (*v), "=r" (ok)
		:
		: "cc");

		return ok;
		}

		static inline bool __must_check arch_get_random_long(unsigned long *v)
		{
		return false;
		}

		static inline bool __must_check arch_get_random_int(unsigned int *v)
		{
		return false;
		}

		static inline bool __must_check arch_get_random_seed_long(unsigned long *v)
		{
		/*
		* Only support the generic interface after we have detected
		* the system wide capability, avoiding complexity with the
		* cpufeature code and with potential scheduling between CPUs
		* with and without the feature.
		*/
		if (!cpus_have_const_cap(ARM64_HAS_RNG))
		return false;

		return __arm64_rndr(v);
		}


		static inline bool __must_check arch_get_random_seed_int(unsigned int *v)
		{
		unsigned long val;
		bool ok = arch_get_random_seed_long(&val);

		*v = val;
		return ok;
		}

		static inline bool __init __early_cpu_has_rndr(void)
		{
		/* Open code as we run prior to the first call to cpufeature. */
		unsigned long ftr = read_sysreg_s(SYS_ID_AA64ISAR0_EL1);
		return (ftr >> ID_AA64ISAR0_RNDR_SHIFT) & 0xf;
		}

		#else

		static inline bool __arm64_rndr(unsigned long *v) { return false; }
		static inline bool __init __early_cpu_has_rndr(void) { return false; }

		#endif /* CONFIG_ARCH_RANDOM */
		#endif /* _ASM_ARCHRANDOM_H */

arch/arm64/include/asm/cpucaps.h

+2 −1

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		@@ -57,7 +57,8 @@
		#define ARM64_WORKAROUND_1542419 47
		#define ARM64_WORKAROUND_SPECULATIVE_AT_NVHE 48
		#define ARM64_HAS_E0PD 49
		#define ARM64_HAS_RNG 50

		#define ARM64_NCAPS 50
		#define ARM64_NCAPS 51

		#endif /* __ASM_CPUCAPS_H */

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