Commit bbf5f6c3 authored by Anthony Koo's avatar Anthony Koo Committed by Alex Deucher
Browse files

drm/amd/display: Split program front end part that occur outside lock 



[Why]
Eventually want to lock at a higher level in stack.
To do this, we need to be able to isolate the parts that need to be done
after pipe unlock.

[How]
Split out programming that is done post unlock.

Signed-off-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0b464c85

drivers/gpu/drm/amd/display/dc/core/dc.c

+19 −5
Original line number Diff line number Diff line
@@ -786,11 +786,15 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) 
		if (should_disable && old_stream) {

			dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);

			disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);

			if (dc->hwss.apply_ctx_for_surface)

			if (dc->hwss.apply_ctx_for_surface) {

				dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);

				dc->hwss.post_unlock_program_front_end(dc, dangling_context);

			}

		if (dc->hwss.program_front_end_for_ctx)

			if (dc->hwss.program_front_end_for_ctx) {

				dc->hwss.program_front_end_for_ctx(dc, dangling_context);

				dc->hwss.post_unlock_program_front_end(dc, dangling_context);

			}

		}

	}



	current_ctx = dc->current_state;
@@ -1219,6 +1223,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c 
				dc, context->streams[i],

				context->stream_status[i].plane_count,

				context); /* use new pipe config in new context */

			dc->hwss.post_unlock_program_front_end(dc, context);

		}



	/* Program hardware */
@@ -1238,19 +1243,24 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c 
	}



	/* Program all planes within new context*/

	if (dc->hwss.program_front_end_for_ctx)

	if (dc->hwss.program_front_end_for_ctx) {

		dc->hwss.program_front_end_for_ctx(dc, context);

		dc->hwss.post_unlock_program_front_end(dc, context);

	}



	for (i = 0; i < context->stream_count; i++) {

		const struct dc_link *link = context->streams[i]->link;



		if (!context->streams[i]->mode_changed)

			continue;



		if (dc->hwss.apply_ctx_for_surface)

		if (dc->hwss.apply_ctx_for_surface) {

			dc->hwss.apply_ctx_for_surface(

					dc, context->streams[i],

					context->stream_status[i].plane_count,

					context);

			dc->hwss.post_unlock_program_front_end(dc, context);

		}



		/*

		 * enable stereo
@@ -2183,6 +2193,7 @@ static void commit_planes_for_stream(struct dc *dc, 
		if (dc->hwss.program_front_end_for_ctx)

			dc->hwss.program_front_end_for_ctx(dc, context);



		dc->hwss.post_unlock_program_front_end(dc, context);

		return;

	}
@@ -2315,6 +2326,9 @@ static void commit_planes_for_stream(struct dc *dc, 
		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);

	}



	if (update_type != UPDATE_TYPE_FAST)

		dc->hwss.post_unlock_program_front_end(dc, context);



	// Fire manual trigger only when bottom plane is flipped

	for (j = 0; j < dc->res_pool->pipe_count; j++) {

		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+6 −0
Original line number Diff line number Diff line
@@ -2621,6 +2621,11 @@ static void dce110_apply_ctx_for_surface( 
		enable_fbc(dc, context);

}



static void dce110_post_unlock_program_front_end(

		struct dc *dc,

		struct dc_state *context)

{

}

static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)

{

	struct dce_hwseq *hws = dc->hwseq;
@@ -2722,6 +2727,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { 
	.init_hw = init_hw,

	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,

	.apply_ctx_for_surface = dce110_apply_ctx_for_surface,

	.post_unlock_program_front_end = dce110_post_unlock_program_front_end,

	.update_plane_addr = update_plane_addr,

	.update_pending_status = dce110_update_pending_status,

	.enable_accelerated_mode = dce110_enable_accelerated_mode,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+33 −6
Original line number Diff line number Diff line
@@ -2512,7 +2512,6 @@ void dcn10_apply_ctx_for_surface( 
	int i;

	struct timing_generator *tg;

	uint32_t underflow_check_delay_us;

	bool removed_pipe[4] = { false };

	bool interdependent_update = false;

	struct pipe_ctx *top_pipe_to_program =

			dcn10_find_top_pipe_for_stream(dc, context, stream);
@@ -2552,6 +2551,9 @@ void dcn10_apply_ctx_for_surface( 
		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];

		struct pipe_ctx *old_pipe_ctx =

				&dc->current_state->res_ctx.pipe_ctx[i];



		pipe_ctx->update_flags.raw = 0;



		/*

		 * Powergate reused pipes that are not powergated

		 * fairly hacky right now, using opp_id as indicator
@@ -2571,7 +2573,7 @@ void dcn10_apply_ctx_for_surface( 
		    old_pipe_ctx->stream_res.tg == tg) {



			hws->funcs.plane_atomic_disconnect(dc, old_pipe_ctx);

			removed_pipe[i] = true;

			pipe_ctx->update_flags.bits.disable = 1;



			DC_LOG_DC("Reset mpcc for pipe %d\n",

					old_pipe_ctx->pipe_idx);
@@ -2602,16 +2604,41 @@ void dcn10_apply_ctx_for_surface( 
		dcn10_lock_all_pipes(dc, context, false);

	else

		dcn10_pipe_control_lock(dc, top_pipe_to_program, false);

}



void dcn10_post_unlock_program_front_end(

		struct dc *dc,

		struct dc_state *context)

{

	int i, j;



	DC_LOGGER_INIT(dc->ctx->logger);



	if (num_planes == 0)

		false_optc_underflow_wa(dc, stream, tg);

	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];



		if (!pipe_ctx->top_pipe &&

			!pipe_ctx->prev_odm_pipe &&

			pipe_ctx->stream) {

			struct dc_stream_status *stream_status = NULL;

			struct timing_generator *tg = pipe_ctx->stream_res.tg;



			for (j = 0; j < context->stream_count; j++) {

				if (pipe_ctx->stream == context->streams[j])

					stream_status = &context->stream_status[j];

			}



			if (context->stream_status[i].plane_count == 0)

				false_optc_underflow_wa(dc, pipe_ctx->stream, tg);

		}

	}



	for (i = 0; i < dc->res_pool->pipe_count; i++)

		if (removed_pipe[i])

		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)

			dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);



	for (i = 0; i < dc->res_pool->pipe_count; i++)

		if (removed_pipe[i]) {

		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) {

			dc->hwss.optimize_bandwidth(dc, context);

			break;

		}

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

+3 −0
Original line number Diff line number Diff line
@@ -75,6 +75,9 @@ void dcn10_apply_ctx_for_surface( 
		const struct dc_stream_state *stream,

		int num_planes,

		struct dc_state *context);

void dcn10_post_unlock_program_front_end(

		struct dc *dc,

		struct dc_state *context);

void dcn10_hubp_pg_control(

		struct dce_hwseq *hws,

		unsigned int hubp_inst,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c

+1 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { 
	.init_hw = dcn10_init_hw,

	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,

	.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,

	.post_unlock_program_front_end = dcn10_post_unlock_program_front_end,

	.update_plane_addr = dcn10_update_plane_addr,

	.update_dchub = dcn10_update_dchub,

	.update_pending_status = dcn10_update_pending_status,

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