dt-bindings: dmaengine: convert Actions Semi Owl SoCs bindings to yaml

* Actions Semi Owl SoCs DMA controller

This binding follows the generic DMA bindings defined in dma.txt.

Required properties:

- compatible: Should be "actions,s900-dma".

- reg: Should contain DMA registers location and length.

- interrupts: Should contain 4 interrupts shared by all channel.

- #dma-cells: Must be <1>. Used to represent the number of integer

              cells in the dmas property of client device.

- dma-channels: Physical channels supported.

- dma-requests: Number of DMA request signals supported by the controller.

                Refer to Documentation/devicetree/bindings/dma/dma.txt

- clocks: Phandle and Specifier of the clock feeding the DMA controller.

Example:

Controller:

                dma: dma-controller@e0260000 {

                        compatible = "actions,s900-dma";

                        reg = <0x0 0xe0260000 0x0 0x1000>;

                        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

                                     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,

                                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,

                                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;

                        #dma-cells = <1>;

                        dma-channels = <12>;

                        dma-requests = <46>;

                        clocks = <&clock CLK_DMAC>;

                };

Client:

DMA clients connected to the Actions Semi Owl SoCs DMA controller must

use the format described in the dma.txt file, using a two-cell specifier

for each channel.

The two cells in order are:

1. A phandle pointing to the DMA controller.

2. The channel id.

uart5: serial@e012a000 {

        ...

        dma-names = "tx", "rx";

        dmas = <&dma 26>, <&dma 27>;

        ...

};

# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/owl-dma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Actions Semi Owl SoCs DMA controller

description: |

  The OWL DMA is a general-purpose direct memory access controller capable of

  supporting 10 and 12 independent DMA channels for S700 and S900 SoCs

  respectively.

maintainers:

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

allOf:

  - $ref: "dma-controller.yaml#"

properties:

  compatible:

    enum:

      - actions,s900-dma

      - actions,s700-dma

  reg:

    maxItems: 1

  interrupts:

    description:

      controller supports 4 interrupts, which are freely assignable to the

      DMA channels.

    maxItems: 4

  "#dma-cells":

    const: 1

  dma-channels:

    maximum: 12

  dma-requests:

    maximum: 46

  clocks:

    maxItems: 1

    description:

      Phandle and Specifier of the clock feeding the DMA controller.

  power-domains:

    maxItems: 1

required:

  - compatible

  - reg

  - interrupts

  - "#dma-cells"

  - dma-channels

  - dma-requests

  - clocks

unevaluatedProperties: false

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    dma: dma-controller@e0260000 {

        compatible = "actions,s900-dma";

        reg = <0xe0260000 0x1000>;

        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,

                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;

        #dma-cells = <1>;

        dma-channels = <12>;

        dma-requests = <46>;

        clocks = <&clock 22>;

    };

...