Commit bbdc070a authored by Dave Gordon's avatar Dave Gordon Committed by Chris Wilson
Browse files

drm/i915: rename macro parameter(ring) to (engine) 



'ring' is an old deprecated term for a GPU engine. Here we make the
terminology more consistent by renaming the 'ring' parameter of lots of
macros that calculate addresses within the MMIO space of an engine.

Signed-off-by: default avatarDave Gordon <david.s.gordon@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469034967-15840-2-git-send-email-david.s.gordon@intel.com


Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 873e8171

drivers/gpu/drm/i915/i915_reg.h

+7 −7
Original line number Diff line number Diff line
@@ -186,13 +186,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define  GEN9_GRDOM_GUC			(1 << 5)

#define  GEN8_GRDOM_MEDIA2		(1 << 7)



#define RING_PP_DIR_BASE(ring)		_MMIO((ring)->mmio_base+0x228)

#define RING_PP_DIR_BASE_READ(ring)	_MMIO((ring)->mmio_base+0x518)

#define RING_PP_DIR_DCLV(ring)		_MMIO((ring)->mmio_base+0x220)

#define RING_PP_DIR_BASE(engine)	_MMIO((engine)->mmio_base+0x228)

#define RING_PP_DIR_BASE_READ(engine)	_MMIO((engine)->mmio_base+0x518)

#define RING_PP_DIR_DCLV(engine)	_MMIO((engine)->mmio_base+0x220)

#define   PP_DIR_DCLV_2G		0xffffffff



#define GEN8_RING_PDP_UDW(ring, n)	_MMIO((ring)->mmio_base+0x270 + (n) * 8 + 4)

#define GEN8_RING_PDP_LDW(ring, n)	_MMIO((ring)->mmio_base+0x270 + (n) * 8)

#define GEN8_RING_PDP_UDW(engine, n)	_MMIO((engine)->mmio_base+0x270 + (n) * 8 + 4)

#define GEN8_RING_PDP_LDW(engine, n)	_MMIO((engine)->mmio_base+0x270 + (n) * 8)



#define GEN8_R_PWR_CLK_STATE		_MMIO(0x20C8)

#define   GEN8_RPCS_ENABLE		(1 << 31)
@@ -1647,7 +1647,7 @@ enum skl_disp_power_wells { 
#define   ARB_MODE_BWGTLB_DISABLE (1<<9)

#define   ARB_MODE_SWIZZLE_BDW	(1<<1)

#define RENDER_HWS_PGA_GEN7	_MMIO(0x04080)

#define RING_FAULT_REG(ring)	_MMIO(0x4094 + 0x100*(ring)->id)

#define RING_FAULT_REG(engine)	_MMIO(0x4094 + 0x100*(engine)->id)

#define   RING_FAULT_GTTSEL_MASK (1<<11)

#define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)

#define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
@@ -1845,7 +1845,7 @@ enum skl_disp_power_wells { 


#define GFX_MODE	_MMIO(0x2520)

#define GFX_MODE_GEN7	_MMIO(0x229c)

#define RING_MODE_GEN7(ring)	_MMIO((ring)->mmio_base+0x29c)

#define RING_MODE_GEN7(engine)	_MMIO((engine)->mmio_base+0x29c)

#define   GFX_RUN_LIST_ENABLE		(1<<15)

#define   GFX_INTERRUPT_STEERING	(1<<14)

#define   GFX_TLB_INVALIDATE_EXPLICIT	(1<<13)

drivers/gpu/drm/i915/intel_lrc.h

+8 −8
Original line number Diff line number Diff line
@@ -29,17 +29,17 @@ 
#define GEN8_LR_CONTEXT_ALIGN 4096



/* Execlists regs */

#define RING_ELSP(ring)				_MMIO((ring)->mmio_base + 0x230)

#define RING_EXECLIST_STATUS_LO(ring)		_MMIO((ring)->mmio_base + 0x234)

#define RING_EXECLIST_STATUS_HI(ring)		_MMIO((ring)->mmio_base + 0x234 + 4)

#define RING_CONTEXT_CONTROL(ring)		_MMIO((ring)->mmio_base + 0x244)

#define RING_ELSP(engine)			_MMIO((engine)->mmio_base + 0x230)

#define RING_EXECLIST_STATUS_LO(engine)		_MMIO((engine)->mmio_base + 0x234)

#define RING_EXECLIST_STATUS_HI(engine)		_MMIO((engine)->mmio_base + 0x234 + 4)

#define RING_CONTEXT_CONTROL(engine)		_MMIO((engine)->mmio_base + 0x244)

#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)

#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)

#define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)

#define RING_CONTEXT_STATUS_BUF_BASE(ring)	_MMIO((ring)->mmio_base + 0x370)

#define RING_CONTEXT_STATUS_BUF_LO(ring, i)	_MMIO((ring)->mmio_base + 0x370 + (i) * 8)

#define RING_CONTEXT_STATUS_BUF_HI(ring, i)	_MMIO((ring)->mmio_base + 0x370 + (i) * 8 + 4)

#define RING_CONTEXT_STATUS_PTR(ring)		_MMIO((ring)->mmio_base + 0x3a0)

#define RING_CONTEXT_STATUS_BUF_BASE(engine)	_MMIO((engine)->mmio_base + 0x370)

#define RING_CONTEXT_STATUS_BUF_LO(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8)

#define RING_CONTEXT_STATUS_BUF_HI(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)

#define RING_CONTEXT_STATUS_PTR(engine)		_MMIO((engine)->mmio_base + 0x3a0)



/* The docs specify that the write pointer wraps around after 5h, "After status

 * is written out to the last available status QW at offset 5h, this pointer

drivers/gpu/drm/i915/intel_ringbuffer.h

+12 −12
Original line number Diff line number Diff line
@@ -31,23 +31,23 @@ struct intel_hw_status_page { 
	struct		drm_i915_gem_object *obj;

};



#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))

#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)

#define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))

#define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)



#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))

#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)

#define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))

#define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)



#define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))

#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)

#define I915_READ_HEAD(engine)  I915_READ(RING_HEAD((engine)->mmio_base))

#define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)



#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))

#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)

#define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))

#define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)



#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))

#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)

#define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))

#define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)



#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))

#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)

#define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))

#define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)



/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to

 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.

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