Commit bba072df authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Thomas Gleixner:
 "A couple of fixes and updates related to x86:

   - Fix the W+X check regression on XEN

   - The real fix for the low identity map trainwreck

   - Probe legacy PIC early instead of unconditionally allocating legacy
     irqs

   - Add cpu verification to long mode entry

   - Adjust the cache topology to AMD Fam17H systems

   - Let Merrifield use the TSC across S3"

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu: Call verify_cpu() after having entered long mode too
  x86/setup: Fix low identity map for >= 2GB kernel range
  x86/mm: Skip the hypervisor range when walking PGD
  x86/AMD: Fix last level cache topology for AMD Fam17h systems
  x86/irq: Probe for PIC presence before allocating descs for legacy IRQs
  x86/cpu/intel: Enable X86_FEATURE_NONSTOP_TSC_S3 for Merrifield
parents 511601bd 04633df0

arch/x86/include/asm/i8259.h

+1 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ struct legacy_pic { 
	void (*mask_all)(void);

	void (*restore_mask)(void);

	void (*init)(int auto_eoi);

	int (*probe)(void);

	int (*irq_pending)(unsigned int irq);

	void (*make_irq)(unsigned int irq);

};

arch/x86/kernel/apic/vector.c

+5 −1
Original line number Diff line number Diff line
@@ -361,7 +361,11 @@ int __init arch_probe_nr_irqs(void) 
	if (nr < nr_irqs)

		nr_irqs = nr;



	return nr_legacy_irqs();

	/*

	 * We don't know if PIC is present at this point so we need to do

	 * probe() to get the right number of legacy IRQs.

	 */

	return legacy_pic->probe();

}



#ifdef	CONFIG_X86_IO_APIC

arch/x86/kernel/cpu/amd.c

+13 −0
Original line number Diff line number Diff line
@@ -352,6 +352,7 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c) 
#ifdef CONFIG_SMP

	unsigned bits;

	int cpu = smp_processor_id();

	unsigned int socket_id, core_complex_id;



	bits = c->x86_coreid_bits;

	/* Low order bits define the core id (index of core in socket) */
@@ -361,6 +362,18 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c) 
	/* use socket ID also for last level cache */

	per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;

	amd_get_topology(c);



	/*

	 * Fix percpu cpu_llc_id here as LLC topology is different

	 * for Fam17h systems.

	 */

	 if (c->x86 != 0x17 || !cpuid_edx(0x80000006))

		return;



	socket_id	= (c->apicid >> bits) - 1;

	core_complex_id	= (c->apicid & ((1 << bits) - 1)) >> 3;



	per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;

#endif

}

arch/x86/kernel/cpu/intel.c

+1 −0
Original line number Diff line number Diff line
@@ -97,6 +97,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) 
		switch (c->x86_model) {

		case 0x27:	/* Penwell */

		case 0x35:	/* Cloverview */

		case 0x4a:	/* Merrifield */

			set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);

			break;

		default:

arch/x86/kernel/head_64.S

+8 −0
Original line number Diff line number Diff line
@@ -65,6 +65,9 @@ startup_64: 
	 * tables and then reload them.

	 */



	/* Sanitize CPU configuration */

	call verify_cpu



	/*

	 * Compute the delta between the address I am compiled to run at and the

	 * address I am actually running at.
@@ -174,6 +177,9 @@ ENTRY(secondary_startup_64) 
	 * after the boot processor executes this code.

	 */



	/* Sanitize CPU configuration */

	call verify_cpu



	movq	$(init_level4_pgt - __START_KERNEL_map), %rax

1:
@@ -288,6 +294,8 @@ ENTRY(secondary_startup_64) 
	pushq	%rax		# target address in negative space

	lretq



#include "verify_cpu.S"



#ifdef CONFIG_HOTPLUG_CPU

/*

 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set

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