arm64: dts: allwinner: h5: Add device node for Mali-450 GPU

			     <GIC_PPI 10

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

	};

	soc {

		mali: gpu@1e80000 {

			compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";

			reg = <0x01e80000 0x30000>;

			/*

			 * While the datasheet lists an interrupt for the

			 * PMU, the actual silicon does not have the PMU

			 * block. Reads all return zero, and writes are

			 * ignored.

			 */

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "gp",

					  "gpmmu",

					  "pp",

					  "pp0",

					  "ppmmu0",

					  "pp1",

					  "ppmmu1",

					  "pp2",

					  "ppmmu2",

					  "pp3",

					  "ppmmu3",

					  "pmu";

			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;

			clock-names = "bus", "core";

			resets = <&ccu RST_BUS_GPU>;

			assigned-clocks = <&ccu CLK_GPU>;

			assigned-clock-rates = <384000000>;

		};

	};

};

&ccu {