Commit bb302711 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-5.5-1' of... 

Merge tag 'sunxi-clk-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Maxime Ripard:

A few clock patches for sunxi, mostly to export new clocks to the DT,
and fix some issues with the clock tree on the H6.

* tag 'sunxi-clk-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: h3: Export MBUS clock
  clk: sunxi-ng: h6: Allow GPU to change parent rate
  clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL
parents 54ecb8f7 4441b57e

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

+16 −7
Original line number Diff line number Diff line
@@ -203,12 +203,21 @@ static struct ccu_nkmp pll_hsic_clk = { 
 * hardcode it to match with the clock names.

 */

#define SUN50I_H6_PLL_AUDIO_REG		0x078



static struct ccu_sdm_setting pll_audio_sdm_table[] = {

	{ .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 },

	{ .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 },

};



static struct ccu_nm pll_audio_base_clk = {

	.enable		= BIT(31),

	.lock		= BIT(28),

	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),

	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */

	.sdm		= _SUNXI_CCU_SDM(pll_audio_sdm_table,

					 BIT(24), 0x178, BIT(31)),

	.common		= {

		.features	= CCU_FEATURE_SIGMA_DELTA_MOD,

		.reg		= 0x078,

		.hw.init	= CLK_HW_INIT("pll-audio-base", "osc24M",

					      &ccu_nm_ops,
@@ -290,7 +299,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, 
				       0, 3,	/* M */

				       24, 1,	/* mux */

				       BIT(31),	/* gate */

				       0);

				       CLK_SET_RATE_PARENT);



static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",

		      0x67c, BIT(0), 0);
@@ -753,12 +762,12 @@ static const struct clk_hw *clk_parent_pll_audio[] = { 
};



/*

 * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a

 * fixed post-divider 2.

 * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200

 * rates can be set exactly in conjunction with sigma-delta modulation.

 */

static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",

			    clk_parent_pll_audio,

			    8, 1, CLK_SET_RATE_PARENT);

			    24, 1, CLK_SET_RATE_PARENT);

static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",

			    clk_parent_pll_audio,

			    4, 1, CLK_SET_RATE_PARENT);
@@ -1215,12 +1224,12 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev) 
	}



	/*

	 * Force the post-divider of pll-audio to 8 and the output divider

	 * of it to 1, to make the clock name represents the real frequency.

	 * Force the post-divider of pll-audio to 12 and the output divider

	 * of it to 2, so 24576000 and 22579200 rates can be set exactly.

	 */

	val = readl(reg + SUN50I_H6_PLL_AUDIO_REG);

	val &= ~(GENMASK(21, 16) | BIT(0));

	writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG);

	writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG);



	/*

	 * First clock parent (osc32K) is unusable for CEC. But since there

drivers/clk/sunxi-ng/ccu-sun8i-h3.h

+0 −4
Original line number Diff line number Diff line
@@ -48,10 +48,6 @@ 


/* Some more module clocks are exported */



#define CLK_MBUS		113



/* And the GPU module clock is exported */



#define CLK_NUMBER_H3		(CLK_GPU + 1)

#define CLK_NUMBER_H5		(CLK_BUS_SCR1 + 1)

include/dt-bindings/clock/sun8i-h3-ccu.h

+1 −1
Original line number Diff line number Diff line
@@ -143,7 +143,7 @@ 
#define CLK_AVS			110

#define CLK_HDMI		111

#define CLK_HDMI_DDC		112



#define CLK_MBUS		113

#define CLK_GPU			114



/* New clocks imported in H5 */

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