Commit bb067482 authored Sep 01, 2020 by Huang Pei Committed by Thomas Bogendoerfer Sep 03, 2020

MIPS: add missing MSACSR and upper MSA initialization



In cc97ab23 ("MIPS: Simplify FP context initialization), init_fp_ctx
just initialize the fp/msa context, and own_fp_inatomic just restore
FCSR and 64bit FP regs from it, but miss MSACSR and upper MSA regs for
MSA, so MSACSR and MSA upper regs's value from previous task on current
cpu can leak into current task and cause unpredictable behavior when MSA
context not initialized.

Fixes: cc97ab23 ("MIPS: Simplify FP context initialization")
Signed-off-by: Huang Pei <huangpei@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

parent a2319957

arch/mips/kernel/traps.c

+12 −0

Original line number	Diff line number	Diff line
		@@ -1287,6 +1287,18 @@ static int enable_restore_fp_context(int msa)
		err = own_fpu_inatomic(1);
		if (msa && !err) {
		enable_msa();
		/*
		* with MSA enabled, userspace can see MSACSR
		* and MSA regs, but the values in them are from
		* other task before current task, restore them
		* from saved fp/msa context
		*/
		write_msa_csr(current->thread.fpu.msacsr);
		/*
		* own_fpu_inatomic(1) just restore low 64bit,
		* fix the high 64bit
		*/
		init_msa_upper();
		set_thread_flag(TIF_USEDMSA);
		set_thread_flag(TIF_MSA_CTX_LIVE);
		}

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