x86/fpu: Get rid of CONFIG_AS_FXSAVEQ (bae54dc4) · Commits · 戴 / test

arch/x86/Makefile

+0 −1

Original line number	Diff line number	Diff line
		@@ -187,7 +187,6 @@ cfi-sigframe := $(call as-instr,.cfi_startproc\n.cfi_signal_frame\n.cfi_endproc,
		cfi-sections := $(call as-instr,.cfi_sections .debug_frame,-DCONFIG_AS_CFI_SECTIONS=1)

		# does binutils support specific instructions?
		asinstr := $(call as-instr,fxsaveq (%rax),-DCONFIG_AS_FXSAVEQ=1)
		asinstr += $(call as-instr,pshufb %xmm0$(comma)%xmm0,-DCONFIG_AS_SSSE3=1)
		avx_instr := $(call as-instr,vxorps %ymm0$(comma)%ymm1$(comma)%ymm2,-DCONFIG_AS_AVX=1)
		avx2_instr :=$(call as-instr,vpbroadcastb %xmm0$(comma)%ymm1,-DCONFIG_AS_AVX2=1)

arch/x86/include/asm/fpu/internal.h

+6 −44

Original line number	Diff line number	Diff line
		@@ -137,37 +137,25 @@ static inline int copy_fxregs_to_user(struct fxregs_state __user *fx)
		{
		if (IS_ENABLED(CONFIG_X86_32))
		return user_insn(fxsave %[fx], [fx] "=m" (fx), "m" (fx));
		else if (IS_ENABLED(CONFIG_AS_FXSAVEQ))
		else
		return user_insn(fxsaveq %[fx], [fx] "=m" (fx), "m" (fx));

		/* See comment in copy_fxregs_to_kernel() below. */
		return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx));
		}

		static inline void copy_kernel_to_fxregs(struct fxregs_state *fx)
		{
		if (IS_ENABLED(CONFIG_X86_32)) {
		if (IS_ENABLED(CONFIG_X86_32))
		kernel_insn(fxrstor %[fx], "=m" (fx), [fx] "m" (fx));
		} else {
		if (IS_ENABLED(CONFIG_AS_FXSAVEQ)) {
		else
		kernel_insn(fxrstorq %[fx], "=m" (fx), [fx] "m" (fx));
		} else {
		/* See comment in copy_fxregs_to_kernel() below. */
		kernel_insn(rex64/fxrstor (%[fx]), "=m" (fx), [fx] "R" (fx), "m" (fx));
		}
		}
		}

		static inline int copy_user_to_fxregs(struct fxregs_state __user *fx)
		{
		if (IS_ENABLED(CONFIG_X86_32))
		return user_insn(fxrstor %[fx], "=m" (fx), [fx] "m" (fx));
		else if (IS_ENABLED(CONFIG_AS_FXSAVEQ))
		else
		return user_insn(fxrstorq %[fx], "=m" (fx), [fx] "m" (fx));

		/* See comment in copy_fxregs_to_kernel() below. */
		return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx),
		"m" (*fx));
		}

		static inline void copy_kernel_to_fregs(struct fregs_state *fx)
		@@ -184,34 +172,8 @@ static inline void copy_fxregs_to_kernel(struct fpu *fpu)
		{
		if (IS_ENABLED(CONFIG_X86_32))
		asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave));
		else if (IS_ENABLED(CONFIG_AS_FXSAVEQ))
		else
		asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave));
		else {
		/* Using "rex64; fxsave %0" is broken because, if the memory
		* operand uses any extended registers for addressing, a second
		* REX prefix will be generated (to the assembler, rex64
		* followed by semicolon is a separate instruction), and hence
		* the 64-bitness is lost.
		*
		* Using "fxsaveq %0" would be the ideal choice, but is only
		* supported starting with gas 2.16.
		*
		* Using, as a workaround, the properly prefixed form below
		* isn't accepted by any binutils version so far released,
		* complaining that the same type of prefix is used twice if
		* an extended register is needed for addressing (fix submitted
		* to mainline 2005-11-21).
		*
		* asm volatile("rex64/fxsave %0" : "=m" (fpu->state.fxsave));
		*
		* This, however, we can work around by forcing the compiler to
		* select an addressing mode that doesn't require extended
		* registers.
		*/
		asm volatile( "rex64/fxsave (%[fx])"
		: "=m" (fpu->state.fxsave)
		: [fx] "R" (&fpu->state.fxsave));
		}
		}

		/* These macros all use (%edi)/(%rdi) as the single memory argument. */

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