Commit bacada1c authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'intel-pinctrl-v5.4' of... 

Merge tag 'intel-pinctrl-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v5.4

A collection of improvements and fixes for Intel pinctrl drivers
including:

  - Converting drivers to use new devm_platform_ioremap_resource()
    helper function.

  - Make Interrupt Status (IS) register configurable.

  - Allow locked pins to be requested and used as long as they are not
    modified.

  - Fix intel_pinctrl_should_save() to translate pin number to GPIO
    number where needed. This fixes Asus X571GT touchpad
    unresponsiveness issue after suspend/resume cycle.
parents 501398b7 6cb0880f

drivers/pinctrl/intel/pinctrl-baytrail.c

+23 −44
Original line number Diff line number Diff line
@@ -98,13 +98,6 @@ struct byt_gpio_pin_context { 
	u32 val;

};



struct byt_community {

	unsigned int pin_base;

	size_t npins;

	const unsigned int *pad_map;

	void __iomem *reg_base;

};



#define COMMUNITY(p, n, map)		\

	{				\

		.pin_base	= (p),	\
@@ -112,26 +105,14 @@ struct byt_community { 
		.pad_map	= (map),\

	}



struct byt_pinctrl_soc_data {

	const char *uid;

	const struct pinctrl_pin_desc *pins;

	size_t npins;

	const struct intel_pingroup *groups;

	size_t ngroups;

	const struct intel_function *functions;

	size_t nfunctions;

	const struct byt_community *communities;

	size_t ncommunities;

};



struct byt_gpio {

	struct gpio_chip chip;

	struct platform_device *pdev;

	struct pinctrl_dev *pctl_dev;

	struct pinctrl_desc pctl_desc;

	raw_spinlock_t lock;

	const struct byt_pinctrl_soc_data *soc_data;

	struct byt_community *communities_copy;

	const struct intel_pinctrl_soc_data *soc_data;

	struct intel_community *communities_copy;

	struct byt_gpio_pin_context *saved_context;

};
@@ -383,11 +364,11 @@ static const struct intel_function byt_score_functions[] = { 
	FUNCTION("gpio", byt_score_gpio_groups),

};



static const struct byt_community byt_score_communities[] = {

static const struct intel_community byt_score_communities[] = {

	COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),

};



static const struct byt_pinctrl_soc_data byt_score_soc_data = {

static const struct intel_pinctrl_soc_data byt_score_soc_data = {

	.uid		= BYT_SCORE_ACPI_UID,

	.pins		= byt_score_pins,

	.npins		= ARRAY_SIZE(byt_score_pins),
@@ -496,11 +477,11 @@ static const struct intel_function byt_sus_functions[] = { 
	FUNCTION("gpio", byt_sus_gpio_groups),

};



static const struct byt_community byt_sus_communities[] = {

static const struct intel_community byt_sus_communities[] = {

	COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),

};



static const struct byt_pinctrl_soc_data byt_sus_soc_data = {

static const struct intel_pinctrl_soc_data byt_sus_soc_data = {

	.uid		= BYT_SUS_ACPI_UID,

	.pins		= byt_sus_pins,

	.npins		= ARRAY_SIZE(byt_sus_pins),
@@ -549,11 +530,11 @@ static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = { 
	3, 6, 10, 13, 2, 5, 9, 7,

};



static const struct byt_community byt_ncore_communities[] = {

static const struct intel_community byt_ncore_communities[] = {

	COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),

};



static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {

static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {

	.uid		= BYT_NCORE_ACPI_UID,

	.pins		= byt_ncore_pins,

	.npins		= ARRAY_SIZE(byt_ncore_pins),
@@ -561,17 +542,17 @@ static const struct byt_pinctrl_soc_data byt_ncore_soc_data = { 
	.ncommunities	= ARRAY_SIZE(byt_ncore_communities),

};



static const struct byt_pinctrl_soc_data *byt_soc_data[] = {

static const struct intel_pinctrl_soc_data *byt_soc_data[] = {

	&byt_score_soc_data,

	&byt_sus_soc_data,

	&byt_ncore_soc_data,

	NULL

};



static struct byt_community *byt_get_community(struct byt_gpio *vg,

static struct intel_community *byt_get_community(struct byt_gpio *vg,

						 unsigned int pin)

{

	struct byt_community *comm;

	struct intel_community *comm;

	int i;



	for (i = 0; i < vg->soc_data->ncommunities; i++) {
@@ -586,7 +567,7 @@ static struct byt_community *byt_get_community(struct byt_gpio *vg, 
static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,

				  int reg)

{

	struct byt_community *comm = byt_get_community(vg, offset);

	struct intel_community *comm = byt_get_community(vg, offset);

	u32 reg_offset;



	if (!comm)
@@ -605,7 +586,7 @@ static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset, 
		break;

	}



	return comm->reg_base + reg_offset + reg;

	return comm->pad_regs + reg_offset + reg;

}



static int byt_get_groups_count(struct pinctrl_dev *pctldev)
@@ -1211,7 +1192,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 
	u32 conf0, val;



	for (i = 0; i < vg->soc_data->npins; i++) {

		const struct byt_community *comm;

		const struct intel_community *comm;

		const char *pull_str = NULL;

		const char *pull = NULL;

		void __iomem *reg;
@@ -1566,7 +1547,7 @@ static int byt_gpio_probe(struct byt_gpio *vg) 
}



static int byt_set_soc_data(struct byt_gpio *vg,

			    const struct byt_pinctrl_soc_data *soc_data)

			    const struct intel_pinctrl_soc_data *soc_data)

{

	int i;
@@ -1579,15 +1560,13 @@ static int byt_set_soc_data(struct byt_gpio *vg, 
		return -ENOMEM;



	for (i = 0; i < soc_data->ncommunities; i++) {

		struct byt_community *comm = vg->communities_copy + i;

		struct resource *mem_rc;

		struct intel_community *comm = vg->communities_copy + i;



		*comm = vg->soc_data->communities[i];



		mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0);

		comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc);

		if (IS_ERR(comm->reg_base))

			return PTR_ERR(comm->reg_base);

		comm->pad_regs = devm_platform_ioremap_resource(vg->pdev, 0);

		if (IS_ERR(comm->pad_regs))

			return PTR_ERR(comm->pad_regs);

	}



	return 0;
@@ -1601,8 +1580,8 @@ static const struct acpi_device_id byt_gpio_acpi_match[] = { 


static int byt_pinctrl_probe(struct platform_device *pdev)

{

	const struct byt_pinctrl_soc_data *soc_data = NULL;

	const struct byt_pinctrl_soc_data **soc_table;

	const struct intel_pinctrl_soc_data *soc_data = NULL;

	const struct intel_pinctrl_soc_data **soc_table;

	struct acpi_device *acpi_dev;

	struct byt_gpio *vg;

	int i, ret;
@@ -1611,7 +1590,7 @@ static int byt_pinctrl_probe(struct platform_device *pdev) 
	if (!acpi_dev)

		return -ENODEV;



	soc_table = (const struct byt_pinctrl_soc_data **)device_get_match_data(&pdev->dev);

	soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(&pdev->dev);



	for (i = 0; soc_table[i]; i++) {

		if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {

drivers/pinctrl/intel/pinctrl-broxton.c

+3 −1
Original line number Diff line number Diff line
@@ -15,8 +15,9 @@ 
#include "pinctrl-intel.h"



#define BXT_PAD_OWN	0x020

#define BXT_HOSTSW_OWN	0x080

#define BXT_PADCFGLOCK	0x060

#define BXT_HOSTSW_OWN	0x080

#define BXT_GPI_IS	0x100

#define BXT_GPI_IE	0x110



#define BXT_COMMUNITY(s, e)				\
@@ -24,6 +25,7 @@ 
		.padown_offset = BXT_PAD_OWN,		\

		.padcfglock_offset = BXT_PADCFGLOCK,	\

		.hostown_offset = BXT_HOSTSW_OWN,	\

		.is_offset = BXT_GPI_IS,		\

		.ie_offset = BXT_GPI_IE,		\

		.gpp_size = 32,                         \

		.pin_base = (s),			\

drivers/pinctrl/intel/pinctrl-cannonlake.c

+2 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#define CNL_PADCFGLOCK		0x080

#define CNL_LP_HOSTSW_OWN	0x0b0

#define CNL_H_HOSTSW_OWN	0x0c0

#define CNL_GPI_IS		0x100

#define CNL_GPI_IE		0x120



#define CNL_GPP(r, s, e, g)				\
@@ -37,6 +38,7 @@ 
		.padown_offset = CNL_PAD_OWN,		\

		.padcfglock_offset = CNL_PADCFGLOCK,	\

		.hostown_offset = (o),			\

		.is_offset = CNL_GPI_IS,		\

		.ie_offset = CNL_GPI_IE,		\

		.pin_base = (s),			\

		.npins = ((e) - (s) + 1),		\

drivers/pinctrl/intel/pinctrl-cherryview.c

+2 −6
Original line number Diff line number Diff line
@@ -1667,7 +1667,6 @@ static int chv_pinctrl_probe(struct platform_device *pdev) 
{

	struct chv_pinctrl *pctrl;

	struct acpi_device *adev;

	struct resource *res;

	acpi_status status;

	int ret, irq, i;
@@ -1697,16 +1696,13 @@ static int chv_pinctrl_probe(struct platform_device *pdev) 
		return -ENOMEM;

#endif



	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	pctrl->regs = devm_ioremap_resource(&pdev->dev, res);

	pctrl->regs = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(pctrl->regs))

		return PTR_ERR(pctrl->regs);



	irq = platform_get_irq(pdev, 0);

	if (irq < 0) {

		dev_err(&pdev->dev, "failed to get interrupt number\n");

	if (irq < 0)

		return irq;

	}



	pctrl->pctldesc = chv_pinctrl_desc;

	pctrl->pctldesc.name = dev_name(&pdev->dev);

drivers/pinctrl/intel/pinctrl-denverton.c

+28 −25
Original line number Diff line number Diff line
@@ -15,8 +15,9 @@ 
#include "pinctrl-intel.h"



#define DNV_PAD_OWN	0x020

#define DNV_HOSTSW_OWN	0x0C0

#define DNV_PADCFGLOCK	0x090

#define DNV_HOSTSW_OWN	0x0C0

#define DNV_GPI_IS	0x100

#define DNV_GPI_IE	0x120



#define DNV_GPP(n, s, e)				\
@@ -32,6 +33,7 @@ 
		.padown_offset = DNV_PAD_OWN,		\

		.padcfglock_offset = DNV_PADCFGLOCK,	\

		.hostown_offset = DNV_HOSTSW_OWN,	\

		.is_offset = DNV_GPI_IS,		\

		.ie_offset = DNV_GPI_IE,		\

		.pin_base = (s),			\

		.npins = ((e) - (s) + 1),		\
@@ -39,6 +41,7 @@ 
		.ngpps = ARRAY_SIZE(g),			\

	}



/* Denverton */

static const struct pinctrl_pin_desc dnv_pins[] = {

	/* North ALL */

	PINCTRL_PIN(0, "GBE0_SDP0"),
@@ -59,7 +62,7 @@ static const struct pinctrl_pin_desc dnv_pins[] = { 
	PINCTRL_PIN(15, "NCSI_CLK_IN"),

	PINCTRL_PIN(16, "NCSI_RXD1"),

	PINCTRL_PIN(17, "NCSI_CRS_DV"),

	PINCTRL_PIN(18, "NCSI_ARB_IN"),

	PINCTRL_PIN(18, "IDSLDO_VID_TICKLE"),

	PINCTRL_PIN(19, "NCSI_TX_EN"),

	PINCTRL_PIN(20, "NCSI_TXD0"),

	PINCTRL_PIN(21, "NCSI_TXD1"),
@@ -68,14 +71,14 @@ static const struct pinctrl_pin_desc dnv_pins[] = { 
	PINCTRL_PIN(24, "GBE0_LED1"),

	PINCTRL_PIN(25, "GBE1_LED0"),

	PINCTRL_PIN(26, "GBE1_LED1"),

	PINCTRL_PIN(27, "GPIO_0"),

	PINCTRL_PIN(27, "SPARE_0"),

	PINCTRL_PIN(28, "PCIE_CLKREQ0_N"),

	PINCTRL_PIN(29, "PCIE_CLKREQ1_N"),

	PINCTRL_PIN(30, "PCIE_CLKREQ2_N"),

	PINCTRL_PIN(31, "PCIE_CLKREQ3_N"),

	PINCTRL_PIN(32, "PCIE_CLKREQ4_N"),

	PINCTRL_PIN(33, "GPIO_1"),

	PINCTRL_PIN(34, "GPIO_2"),

	PINCTRL_PIN(33, "GBE_MDC"),

	PINCTRL_PIN(34, "GBE_MDIO"),

	PINCTRL_PIN(35, "SVID_ALERT_N"),

	PINCTRL_PIN(36, "SVID_DATA"),

	PINCTRL_PIN(37, "SVID_CLK"),
@@ -102,15 +105,15 @@ static const struct pinctrl_pin_desc dnv_pins[] = { 
	PINCTRL_PIN(57, "DFX_PORT14"),

	PINCTRL_PIN(58, "DFX_PORT15"),

	/* South GPP0 */

	PINCTRL_PIN(59, "GPIO_12"),

	PINCTRL_PIN(60, "SMB5_GBE_ALRT_N"),

	PINCTRL_PIN(59, "SPI_TPM_CS_N"),

	PINCTRL_PIN(60, "UART2_CTS"),

	PINCTRL_PIN(61, "PCIE_CLKREQ5_N"),

	PINCTRL_PIN(62, "PCIE_CLKREQ6_N"),

	PINCTRL_PIN(63, "PCIE_CLKREQ7_N"),

	PINCTRL_PIN(64, "UART0_RXD"),

	PINCTRL_PIN(65, "UART0_TXD"),

	PINCTRL_PIN(66, "SMB5_GBE_CLK"),

	PINCTRL_PIN(67, "SMB5_GBE_DATA"),

	PINCTRL_PIN(66, "CPU_RESET_N"),

	PINCTRL_PIN(67, "NMI"),

	PINCTRL_PIN(68, "ERROR2_N"),

	PINCTRL_PIN(69, "ERROR1_N"),

	PINCTRL_PIN(70, "ERROR0_N"),
@@ -129,20 +132,20 @@ static const struct pinctrl_pin_desc dnv_pins[] = { 
	PINCTRL_PIN(83, "USB_OC0_N"),

	PINCTRL_PIN(84, "FLEX_CLK_SE0"),

	PINCTRL_PIN(85, "FLEX_CLK_SE1"),

	PINCTRL_PIN(86, "GPIO_4"),

	PINCTRL_PIN(87, "GPIO_5"),

	PINCTRL_PIN(88, "GPIO_6"),

	PINCTRL_PIN(89, "GPIO_7"),

	PINCTRL_PIN(86, "SPARE_4"),

	PINCTRL_PIN(87, "SMB3_IE0_CLK"),

	PINCTRL_PIN(88, "SMB3_IE0_DATA"),

	PINCTRL_PIN(89, "SMB3_IE0_ALRT_N"),

	PINCTRL_PIN(90, "SATA0_LED_N"),

	PINCTRL_PIN(91, "SATA1_LED_N"),

	PINCTRL_PIN(92, "SATA_PDETECT0"),

	PINCTRL_PIN(93, "SATA_PDETECT1"),

	PINCTRL_PIN(94, "SATA0_SDOUT"),

	PINCTRL_PIN(95, "SATA1_SDOUT"),

	PINCTRL_PIN(94, "UART1_RTS"),

	PINCTRL_PIN(95, "UART1_CTS"),

	PINCTRL_PIN(96, "UART1_RXD"),

	PINCTRL_PIN(97, "UART1_TXD"),

	PINCTRL_PIN(98, "GPIO_8"),

	PINCTRL_PIN(99, "GPIO_9"),

	PINCTRL_PIN(98, "SPARE_8"),

	PINCTRL_PIN(99, "SPARE_9"),

	PINCTRL_PIN(100, "TCK"),

	PINCTRL_PIN(101, "TRST_N"),

	PINCTRL_PIN(102, "TMS"),
@@ -150,11 +153,11 @@ static const struct pinctrl_pin_desc dnv_pins[] = { 
	PINCTRL_PIN(104, "TDO"),

	PINCTRL_PIN(105, "CX_PRDY_N"),

	PINCTRL_PIN(106, "CX_PREQ_N"),

	PINCTRL_PIN(107, "CTBTRIGINOUT"),

	PINCTRL_PIN(108, "CTBTRIGOUT"),

	PINCTRL_PIN(109, "DFX_SPARE2"),

	PINCTRL_PIN(110, "DFX_SPARE3"),

	PINCTRL_PIN(111, "DFX_SPARE4"),

	PINCTRL_PIN(107, "TAP1_TCK"),

	PINCTRL_PIN(108, "TAP1_TRST_N"),

	PINCTRL_PIN(109, "TAP1_TMS"),

	PINCTRL_PIN(110, "TAP1_TDI"),

	PINCTRL_PIN(111, "TAP1_TDO"),

	/* South GPP1 */

	PINCTRL_PIN(112, "SUSPWRDNACK"),

	PINCTRL_PIN(113, "PMU_SUSCLK"),
@@ -183,8 +186,8 @@ static const struct pinctrl_pin_desc dnv_pins[] = { 
	PINCTRL_PIN(136, "ESPI_CLK"),

	PINCTRL_PIN(137, "ESPI_RST_N"),

	PINCTRL_PIN(138, "ESPI_ALRT0_N"),

	PINCTRL_PIN(139, "GPIO_10"),

	PINCTRL_PIN(140, "GPIO_11"),

	PINCTRL_PIN(139, "ESPI_CS1_N"),

	PINCTRL_PIN(140, "ESPI_ALRT1_N"),

	PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"),

	PINCTRL_PIN(142, "EMMC_CMD"),

	PINCTRL_PIN(143, "EMMC_STROBE"),
@@ -197,7 +200,7 @@ static const struct pinctrl_pin_desc dnv_pins[] = { 
	PINCTRL_PIN(150, "EMMC_D5"),

	PINCTRL_PIN(151, "EMMC_D6"),

	PINCTRL_PIN(152, "EMMC_D7"),

	PINCTRL_PIN(153, "GPIO_3"),

	PINCTRL_PIN(153, "SPARE_3"),

};



static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 };

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