Commit bac51183 authored by Tian Tao's avatar Tian Tao Committed by Xinliang Liu
Browse files

drm/hisilicon: Add new clock/resolution configurations 



Add the three new pll config for corresponding resolution 1440x900 and
1600x900, 640x480 for hibmc

Signed-off-by: default avatarTian Tao <tiantao6@hisilicon.com>
Signed-off-by: default avatarGong junjie <gongjunjie2@huawei.com>
Signed-off-by: default avatarXinliang Liu <xinliang.liu@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/1577774571-60493-1-git-send-email-tiantao6@hisilicon.com
parent e086558a

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c

+3 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ struct hibmc_dislay_pll_config { 
};



static const struct hibmc_dislay_pll_config hibmc_pll_table[] = {

	{640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ},

	{800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ},

	{1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ},

	{1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ},
@@ -47,6 +48,8 @@ static const struct hibmc_dislay_pll_config hibmc_pll_table[] = { 
	{1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ},

	{1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},

	{1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},

	{1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ},

	{1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},

	{1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ},

	{1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ},

	{1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ},

drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h

+2 −0
Original line number Diff line number Diff line
@@ -179,6 +179,7 @@ 
#define CRT_PLL1_HS_74MHZ			0x23941dc2

#define CRT_PLL1_HS_80MHZ			0x23941001

#define CRT_PLL1_HS_80MHZ_1152			0x23540fc2

#define CRT_PLL1_HS_106MHZ			0x237C1641

#define CRT_PLL1_HS_108MHZ			0x23b41b01

#define CRT_PLL1_HS_162MHZ			0x23480681

#define CRT_PLL1_HS_148MHZ			0x23541dc2
@@ -191,6 +192,7 @@ 
#define CRT_PLL2_HS_78MHZ			0x50E147AE

#define CRT_PLL2_HS_74MHZ			0x602B6AE7

#define CRT_PLL2_HS_80MHZ			0x70000000

#define CRT_PLL2_HS_106MHZ			0x0075c28f

#define CRT_PLL2_HS_108MHZ			0x80000000

#define CRT_PLL2_HS_162MHZ			0xA0000000

#define CRT_PLL2_HS_148MHZ			0xB0CCCCCD

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