Commit ba9d0fd0 authored by Jarkko Nikula's avatar Jarkko Nikula Committed by Takashi Iwai
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ALSA: ASoC: OMAP: Fix DSP DAI format in McBSP DAI driver 



Fix word clock length which must equal to one bit clock cycle in DSP mode.
Surprisingly McBSP is able synchronize into wrong length when it's
slave but e.g. TLV320AIC33 codec in slave configuration is outputting
some amount of noise if word clock length is longer than one bit clock
cycle.

Fix also bit clock and frame sync polarities in DSP mode since they are
opposite from I2S.

Signed-off-by: default avatarJarkko Nikula <jarkko.nikula@nokia.com>
Cc: Arun KS <arunks@mistralsolutions.com>
Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
parent 7c2dfee8

sound/soc/omap/omap-mcbsp.c

+20 −4
Original line number Original line Diff line number Diff line
@@ -43,6 +43,7 @@ 
struct omap_mcbsp_data {

struct omap_mcbsp_data {

	unsigned int			bus_id;

	unsigned int			bus_id;

	struct omap_mcbsp_reg_cfg	regs;

	struct omap_mcbsp_reg_cfg	regs;

	unsigned int			fmt;

	/*

	/*

	 * Flags indicating is the bus already activated and configured by

	 * Flags indicating is the bus already activated and configured by

	 * another substream

	 * another substream
@@ -200,6 +201,7 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, 
	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);

	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);

	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;

	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;

	int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;

	int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;

	int wlen;

	unsigned long port;

	unsigned long port;





	if (cpu_class_is_omap1()) {

	if (cpu_class_is_omap1()) {
@@ -244,19 +246,29 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, 
	switch (params_format(params)) {

	switch (params_format(params)) {

	case SNDRV_PCM_FORMAT_S16_LE:

	case SNDRV_PCM_FORMAT_S16_LE:

		/* Set word lengths */

		/* Set word lengths */

		wlen = 16;

		regs->rcr2	|= RWDLEN2(OMAP_MCBSP_WORD_16);

		regs->rcr2	|= RWDLEN2(OMAP_MCBSP_WORD_16);

		regs->rcr1	|= RWDLEN1(OMAP_MCBSP_WORD_16);

		regs->rcr1	|= RWDLEN1(OMAP_MCBSP_WORD_16);

		regs->xcr2	|= XWDLEN2(OMAP_MCBSP_WORD_16);

		regs->xcr2	|= XWDLEN2(OMAP_MCBSP_WORD_16);

		regs->xcr1	|= XWDLEN1(OMAP_MCBSP_WORD_16);

		regs->xcr1	|= XWDLEN1(OMAP_MCBSP_WORD_16);

		/* Set FS period and length in terms of bit clock periods */

		regs->srgr2	|= FPER(16 * 2 - 1);

		regs->srgr1	|= FWID(16 - 1);

		break;

		break;

	default:

	default:

		/* Unsupported PCM format */

		/* Unsupported PCM format */

		return -EINVAL;

		return -EINVAL;

	}

	}





	/* Set FS period and length in terms of bit clock periods */

	switch (mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {

	case SND_SOC_DAIFMT_I2S:

		regs->srgr2	|= FPER(wlen * 2 - 1);

		regs->srgr1	|= FWID(wlen - 1);

		break;

	case SND_SOC_DAIFMT_DSP_A:

		regs->srgr2	|= FPER(wlen * 2 - 1);

		regs->srgr1	|= FWID(0);

		break;

	}



	omap_mcbsp_config(bus_id, &mcbsp_data->regs);

	omap_mcbsp_config(bus_id, &mcbsp_data->regs);

	mcbsp_data->configured = 1;

	mcbsp_data->configured = 1;
@@ -272,10 +284,12 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, 
{

{

	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);

	struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);

	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;

	struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;

	unsigned int temp_fmt = fmt;





	if (mcbsp_data->configured)

	if (mcbsp_data->configured)

		return 0;

		return 0;





	mcbsp_data->fmt = fmt;

	memset(regs, 0, sizeof(*regs));

	memset(regs, 0, sizeof(*regs));

	/* Generic McBSP register settings */

	/* Generic McBSP register settings */

	regs->spcr2	|= XINTM(3) | FREE;

	regs->spcr2	|= XINTM(3) | FREE;
@@ -293,6 +307,8 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, 
		/* 0-bit data delay */

		/* 0-bit data delay */

		regs->rcr2      |= RDATDLY(0);

		regs->rcr2      |= RDATDLY(0);

		regs->xcr2      |= XDATDLY(0);

		regs->xcr2      |= XDATDLY(0);

		/* Invert bit clock and FS polarity configuration for DSP_A */

		temp_fmt ^= SND_SOC_DAIFMT_IB_IF;

		break;

		break;

	default:

	default:

		/* Unsupported data format */

		/* Unsupported data format */
@@ -316,7 +332,7 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, 
	}

	}





	/* Set bit clock (CLKX/CLKR) and FS polarities */

	/* Set bit clock (CLKX/CLKR) and FS polarities */

	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {

	switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {

	case SND_SOC_DAIFMT_NB_NF:

	case SND_SOC_DAIFMT_NB_NF:

		/*

		/*

		 * Normal BCLK + FS.

		 * Normal BCLK + FS.

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