Commit ba95e9bd authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge remote-tracking branch 'arm64/for-next/fixes' into for-next/core 

This is required to solve the conflicts with subsequent merges of two
more errata workaround branches.

* arm64/for-next/fixes:
  arm64: tags: Preserve tags for addresses translated via TTBR1
  arm64: mm: fix inverted PAR_EL1.F check
  arm64: sysreg: fix incorrect definition of SYS_PAR_EL1_F
  arm64: entry.S: Do not preempt from IRQ before all cpufeatures are enabled
  arm64: hibernate: check pgd table allocation
  arm64: cpufeature: Treat ID_AA64ZFR0_EL1 as RAZ when SVE is not enabled
  arm64: Fix kcore macros after 52-bit virtual addressing fallout
  arm64: Allow CAVIUM_TX2_ERRATUM_219 to be selected
  arm64: Avoid Cavium TX2 erratum 219 when switching TTBR
  arm64: Enable workaround for Cavium TX2 erratum 219 when running SMT
  arm64: KVM: Trap VM ops when ARM64_WORKAROUND_CAVIUM_TX2_219_TVM is set
parents 4f5cafb5 777d062e

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -107,6 +107,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Cavium         | ThunderX2 SMMUv3| #126            | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| Cavium         | ThunderX2 Core  | #219            | CAVIUM_TX2_ERRATUM_219      |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585         |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+17 −0
Original line number Diff line number Diff line
@@ -616,6 +616,23 @@ config CAVIUM_ERRATUM_30115 


	  If unsure, say Y.



config CAVIUM_TX2_ERRATUM_219

	bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"

	default y

	help

	  On Cavium ThunderX2, a load, store or prefetch instruction between a

	  TTBR update and the corresponding context synchronizing operation can

	  cause a spurious Data Abort to be delivered to any hardware thread in

	  the CPU core.



	  Work around the issue by avoiding the problematic code sequence and

	  trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The

	  trap handler performs the corresponding register access, skips the

	  instruction and ensures context synchronization by virtue of the

	  exception return.



	  If unsure, say Y.



config QCOM_FALKOR_ERRATUM_1003

	bool "Falkor E1003: Incorrect translation due to ASID change"

	default y

arch/arm64/include/asm/asm-uaccess.h

+3 −4
Original line number Diff line number Diff line
@@ -78,10 +78,9 @@ alternative_else_nop_endif 
/*

 * Remove the address tag from a virtual address, if present.

 */

	.macro	clear_address_tag, dst, addr

	tst	\addr, #(1 << 55)

	bic	\dst, \addr, #(0xff << 56)

	csel	\dst, \dst, \addr, eq

	.macro	untagged_addr, dst, addr

	sbfx	\dst, \addr, #0, #56

	and	\dst, \dst, \addr

	.endm



#endif

arch/arm64/include/asm/cpucaps.h

+3 −1
Original line number Diff line number Diff line
@@ -52,7 +52,9 @@ 
#define ARM64_HAS_IRQ_PRIO_MASKING		42

#define ARM64_HAS_DCPODP			43

#define ARM64_WORKAROUND_1463225		44

#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM	45

#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM	46



#define ARM64_NCAPS				45

#define ARM64_NCAPS				47



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/memory.h

+8 −2
Original line number Diff line number Diff line
@@ -215,12 +215,18 @@ static inline unsigned long kaslr_offset(void) 
 * up with a tagged userland pointer. Clear the tag to get a sane pointer to

 * pass on to access_ok(), for instance.

 */

#define untagged_addr(addr)	\

#define __untagged_addr(addr)	\

	((__force __typeof__(addr))sign_extend64((__force u64)(addr), 55))



#define untagged_addr(addr)	({					\

	u64 __addr = (__force u64)addr;					\

	__addr &= __untagged_addr(__addr);				\

	(__force __typeof__(addr))__addr;				\

})



#ifdef CONFIG_KASAN_SW_TAGS

#define __tag_shifted(tag)	((u64)(tag) << 56)

#define __tag_reset(addr)	untagged_addr(addr)

#define __tag_reset(addr)	__untagged_addr(addr)

#define __tag_get(addr)		(__u8)((u64)(addr) >> 56)

#else

#define __tag_shifted(tag)	0UL

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