Commit ba90e0c9 authored by Roger Quadros's avatar Roger Quadros Committed by Nishanth Menon
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dt-bindings: ti-serdes-mux: Add defines for J7200 SoC 



There are 4 lanes in each J7200 SERDES. Each SERDES lane mux can
select upto 4 different IPs. Define all the possible functions.

Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Reviewed-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarPeter Rosin <peda@axentia.se>
Cc: Peter Rosin <peda@axentia.se>
Link: https://lore.kernel.org/r/20200930122032.23481-2-rogerq@ti.com
parent ffb0024e

include/dt-bindings/mux/ti-serdes.h

+22 −0
Original line number Diff line number Diff line
@@ -68,4 +68,26 @@ 
#define J721E_SERDES4_LANE3_QSGMII_LANE8	0x2

#define J721E_SERDES4_LANE3_IP4_UNUSED		0x3



/* J7200 */



#define J7200_SERDES0_LANE0_QSGMII_LANE3	0x0

#define J7200_SERDES0_LANE0_PCIE1_LANE0		0x1

#define J7200_SERDES0_LANE0_IP3_UNUSED		0x2

#define J7200_SERDES0_LANE0_IP4_UNUSED		0x3



#define J7200_SERDES0_LANE1_QSGMII_LANE4	0x0

#define J7200_SERDES0_LANE1_PCIE1_LANE1		0x1

#define J7200_SERDES0_LANE1_IP3_UNUSED		0x2

#define J7200_SERDES0_LANE1_IP4_UNUSED		0x3



#define J7200_SERDES0_LANE2_QSGMII_LANE1	0x0

#define J7200_SERDES0_LANE2_PCIE1_LANE2		0x1

#define J7200_SERDES0_LANE2_IP3_UNUSED		0x2

#define J7200_SERDES0_LANE2_IP4_UNUSED		0x3



#define J7200_SERDES0_LANE3_QSGMII_LANE2	0x0

#define J7200_SERDES0_LANE3_PCIE1_LANE3		0x1

#define J7200_SERDES0_LANE3_USB			0x2

#define J7200_SERDES0_LANE3_IP4_UNUSED		0x3



#endif /* _DT_BINDINGS_MUX_TI_SERDES */

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