Commit ba8e2b94 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'sunxi-dt-for-4.19' of... 

Merge tag 'sunxi-dt-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

Allwinner DT changes for 4.19

There's a number of additions for the ARMv7 SoCs for this merge window, and
especially:

  - Addition of the system controller for a number of SoCs, as part of the
    VPU effort
  - Addition of the R40 HDMI support
  - Addition of the Mali GPU node for the A10

* tag 'sunxi-dt-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux

: (21 commits)
  ARM: dts: sun4i: Add GPU node
  ARM: dts: sun5i: Fix the SRAM A3-A4 declaration
  ARM: dts: sun8i: r40: Remove unused address-cells/size-cells of dwmac-sun8i
  ARM: dts: sun8i: a83t: Remove unused address-cells/size-cells of dwmac-sun8i
  dt-bindings: net: dwmac-sun8i: Remove unused address-cells/size-cells
  ARM: dts: sun8i: h3: Add SRAM controller node and C1 SRAM region
  ARM: dts: sun8i: a23-a33: Add SRAM controller node and C1 SRAM region
  ARM: dts: sun7i: Add support for the C1 SRAM region with the SRAM controller
  ARM: dts: sun5i: Add support for the C1 SRAM region with the SRAM controller
  ARM: dts: sun7i: Use most-qualified system control compatibles
  ARM: dts: sun5i: Use most-qualified system control compatibles
  ARM: dts: sun4i: Switch to new system control compatible string
  ARM: dts: sun8i: r40: Disable TCONs by default.
  ARM: dts: sun8i: r40: Add missing TCON-TOP - TCON connections
  ARM: dts: sun8i: r40: Remove fallback compatible for TCON TV
  ARM: dts: sun8i: r40: Add mixer ids to TCON TOP
  ARM: dts: sun8i: r40: Remove fallback display engine compatible
  ARM: dts: sun8i: a83t: Add CPU regulator supplies for A83T boards
  ARM: dts: sun8i: r40: Enable HDMI output on BananaPi M2 Ultra
  ARM: dts: sun8i: r40: Add HDMI pipeline
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 9604ff92 c0476a31

Documentation/devicetree/bindings/net/dwmac-sun8i.txt

+0 −8
Original line number Diff line number Diff line
@@ -19,8 +19,6 @@ Required properties: 
- reset-names: must be "stmmaceth"

- phy-mode: See ethernet.txt

- phy-handle: See ethernet.txt

- #address-cells: shall be 1

- #size-cells: shall be 0

- syscon: A phandle to the device containing the EMAC or GMAC clock register



Optional properties:
@@ -86,8 +84,6 @@ emac: ethernet@1c0b000 { 
	reset-names = "stmmaceth";

	clocks = <&ccu CLK_BUS_EMAC>;

	clock-names = "stmmaceth";

	#address-cells = <1>;

	#size-cells = <0>;



	phy-handle = <&int_mii_phy>;

	phy-mode = "mii";
@@ -137,8 +133,6 @@ emac: ethernet@1c0b000 { 
	reset-names = "stmmaceth";

	clocks = <&ccu CLK_BUS_EMAC>;

	clock-names = "stmmaceth";

	#address-cells = <1>;

	#size-cells = <0>;



	phy-handle = <&ext_rgmii_phy>;

	phy-mode = "rgmii";
@@ -191,8 +185,6 @@ emac: ethernet@1c0b000 { 
	reset-names = "stmmaceth";

	clocks = <&ccu CLK_BUS_EMAC>;

	clock-names = "stmmaceth";

	#address-cells = <1>;

	#size-cells = <0>;



	phy-handle = <&ext_rgmii_phy>;

	phy-mode = "rgmii";

arch/arm/boot/dts/sun4i-a10.dtsi

+23 −2
Original line number Diff line number Diff line
@@ -190,8 +190,8 @@ 
		#size-cells = <1>;

		ranges;



		sram-controller@1c00000 {

			compatible = "allwinner,sun4i-a10-sram-controller";

		system-control@1c00000 {

			compatible = "allwinner,sun4i-a10-system-control";

			reg = <0x01c00000 0x30>;

			#address-cells = <1>;

			#size-cells = <1>;
@@ -1001,6 +1001,27 @@ 
			status = "disabled";

		};



		mali: gpu@1c40000 {

			compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";

			reg = <0x01c40000 0x10000>;

			interrupts = <69>,

				     <70>,

				     <71>,

				     <72>,

				     <73>;

			interrupt-names = "gp",

					  "gpmmu",

					  "pp0",

					  "ppmmu0",

					  "pmu";

			clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;

			clock-names = "bus", "core";

			resets = <&ccu RST_GPU>;



			assigned-clocks = <&ccu CLK_GPU>;

			assigned-clock-rates = <384000000>;

		};



		fe0: display-frontend@1e00000 {

			compatible = "allwinner,sun4i-a10-display-frontend";

			reg = <0x01e00000 0x20000>;

arch/arm/boot/dts/sun5i.dtsi

+24 −8
Original line number Diff line number Diff line
@@ -114,8 +114,8 @@ 
		#size-cells = <1>;

		ranges;



		sram-controller@1c00000 {

			compatible = "allwinner,sun4i-a10-sram-controller";

		system-control@1c00000 {

			compatible = "allwinner,sun5i-a13-system-control";

			reg = <0x01c00000 0x30>;

			#address-cells = <1>;

			#size-cells = <1>;
@@ -127,13 +127,14 @@ 
				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0 0x00000000 0xc000>;

			};



				emac_sram: sram-section@8000 {

				compatible = "allwinner,sun4i-a10-sram-a3-a4";

					compatible = "allwinner,sun5i-a13-sram-a3-a4",

						     "allwinner,sun4i-a10-sram-a3-a4";

					reg = <0x8000 0x4000>;

					status = "disabled";

				};

			};



			sram_d: sram@10000 {

				compatible = "mmio-sram";
@@ -143,11 +144,26 @@ 
				ranges = <0 0x00010000 0x1000>;



				otg_sram: sram-section@0 {

					compatible = "allwinner,sun4i-a10-sram-d";

					compatible = "allwinner,sun5i-a13-sram-d",

						     "allwinner,sun4i-a10-sram-d";

					reg = <0x0000 0x1000>;

					status = "disabled";

				};

			};



			sram_c: sram@1d00000 {

				compatible = "mmio-sram";

				reg = <0x01d00000 0xd0000>;

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0 0x01d00000 0xd0000>;



				ve_sram: sram-section@0 {

					compatible = "allwinner,sun5i-a13-sram-c1",

						     "allwinner,sun4i-a10-sram-c1";

					reg = <0x000000 0x80000>;

				};

			};

		};



		dma: dma-controller@1c02000 {

arch/arm/boot/dts/sun6i-a31.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -119,18 +119,48 @@ 
			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <1>;

			clocks = <&ccu CLK_CPU>;

			clock-latency = <244144>; /* 8 32k periods */

			operating-points = <

				/* kHz	  uV */

				1008000	1200000

				864000	1200000

				720000	1100000

				480000	1000000

				>;

			#cooling-cells = <2>;

		};



		cpu@2 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <2>;

			clocks = <&ccu CLK_CPU>;

			clock-latency = <244144>; /* 8 32k periods */

			operating-points = <

				/* kHz	  uV */

				1008000	1200000

				864000	1200000

				720000	1100000

				480000	1000000

				>;

			#cooling-cells = <2>;

		};



		cpu@3 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <3>;

			clocks = <&ccu CLK_CPU>;

			clock-latency = <244144>; /* 8 32k periods */

			operating-points = <

				/* kHz	  uV */

				1008000	1200000

				864000	1200000

				720000	1100000

				480000	1000000

				>;

			#cooling-cells = <2>;

		};

	};

arch/arm/boot/dts/sun7i-a20.dtsi

+34 −4
Original line number Diff line number Diff line
@@ -122,6 +122,19 @@ 
			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <1>;

			clocks = <&ccu CLK_CPU>;

			clock-latency = <244144>; /* 8 32k periods */

			operating-points = <

				/* kHz	  uV */

				960000	1400000

				912000	1400000

				864000	1300000

				720000	1200000

				528000	1100000

				312000	1000000

				144000	1000000

				>;

			#cooling-cells = <2>;

		};

	};
@@ -239,8 +252,9 @@ 
		#size-cells = <1>;

		ranges;



		sram-controller@1c00000 {

			compatible = "allwinner,sun4i-a10-sram-controller";

		system-control@1c00000 {

			compatible = "allwinner,sun7i-a20-system-control",

				     "allwinner,sun4i-a10-system-control";

			reg = <0x01c00000 0x30>;

			#address-cells = <1>;

			#size-cells = <1>;
@@ -254,7 +268,8 @@ 
				ranges = <0 0x00000000 0xc000>;



				emac_sram: sram-section@8000 {

					compatible = "allwinner,sun4i-a10-sram-a3-a4";

					compatible = "allwinner,sun7i-a20-sram-a3-a4",

						     "allwinner,sun4i-a10-sram-a3-a4";

					reg = <0x8000 0x4000>;

					status = "disabled";

				};
@@ -268,11 +283,26 @@ 
				ranges = <0 0x00010000 0x1000>;



				otg_sram: sram-section@0 {

					compatible = "allwinner,sun4i-a10-sram-d";

					compatible = "allwinner,sun7i-a20-sram-d",

						     "allwinner,sun4i-a10-sram-d";

					reg = <0x0000 0x1000>;

					status = "disabled";

				};

			};



			sram_c: sram@1d00000 {

				compatible = "mmio-sram";

				reg = <0x01d00000 0xd0000>;

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0 0x01d00000 0xd0000>;



				ve_sram: sram-section@0 {

					compatible = "allwinner,sun7i-a20-sram-c1",

						     "allwinner,sun4i-a10-sram-c1";

					reg = <0x000000 0x80000>;

				};

			};

		};



		nmi_intc: interrupt-controller@1c00030 {

CRA Git | Maintained and supported by SUSTech CRA and CCSE