Merge remote branch 'korg/drm-radeon-cayman' into drm-core-next (ba77a26c) · Commits · 戴 / test

drivers/gpu/drm/radeon/Makefile

+5 −2

drivers/gpu/drm/radeon/cayman_blit_shaders.c

0 → 100644

+55 −0

Original line number	Original line	Diff line number	Diff line
			/*
			* Copyright 2010 Advanced Micro Devices, Inc.
			*
			* Permission is hereby granted, free of charge, to any person obtaining a
			* copy of this software and associated documentation files (the "Software"),
			* to deal in the Software without restriction, including without limitation
			* the rights to use, copy, modify, merge, publish, distribute, sublicense,
			* and/or sell copies of the Software, and to permit persons to whom the
			* Software is furnished to do so, subject to the following conditions:
			*
			* The above copyright notice and this permission notice (including the next
			* paragraph) shall be included in all copies or substantial portions of the
			* Software.
			*
			* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
			* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
			* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
			* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
			* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
			* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
			* DEALINGS IN THE SOFTWARE.
			*
			* Authors:
			* Alex Deucher <alexander.deucher@amd.com>
			*/

			#include <linux/types.h>
			#include <linux/kernel.h>

			/*
			* evergreen cards need to use the 3D engine to blit data which requires
			* quite a bit of hw state setup. Rather than pull the whole 3D driver
			* (which normally generates the 3D state) into the DRM, we opt to use
			* statically generated state tables. The regsiter state and shaders
			* were hand generated to support blitting functionality. See the 3D
			* driver or documentation for descriptions of the registers and
			* shader instructions.
			*/

			const u32 cayman_default_state[] =
			{
			/* XXX fill in additional blit state */

			0xc0026900,
			0x00000316,
			0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
			0x00000010, /* */

			0xc0026900,
			0x000000d9,
			0x00000000, /* CP_RINGID */
			0x00000000, /* CP_VMID */
			};

			const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);

drivers/gpu/drm/radeon/cayman_blit_shaders.h

0 → 100644

+32 −0

Original line number	Original line	Diff line number	Diff line
			/*
			* Copyright 2010 Advanced Micro Devices, Inc.
			*
			* Permission is hereby granted, free of charge, to any person obtaining a
			* copy of this software and associated documentation files (the "Software"),
			* to deal in the Software without restriction, including without limitation
			* the rights to use, copy, modify, merge, publish, distribute, sublicense,
			* and/or sell copies of the Software, and to permit persons to whom the
			* Software is furnished to do so, subject to the following conditions:
			*
			* The above copyright notice and this permission notice (including the next
			* paragraph) shall be included in all copies or substantial portions of the
			* Software.
			*
			* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
			* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
			* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
			* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
			* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
			* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
			* DEALINGS IN THE SOFTWARE.
			*
			*/

			#ifndef CAYMAN_BLIT_SHADERS_H
			#define CAYMAN_BLIT_SHADERS_H

			extern const u32 cayman_default_state[];

			extern const u32 cayman_default_size;

			#endif

drivers/gpu/drm/radeon/evergreen.c

+8 −8

Original line number	Original line	Diff line number	Diff line
	@@ -804,7 +804,7 @@ void evergreen_bandwidth_update(struct radeon_device *rdev)
	}		}
	}		}

	static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)		int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
	{		{
	unsigned i;		unsigned i;
	u32 tmp;		u32 tmp;
	@@ -957,7 +957,7 @@ void evergreen_agp_enable(struct radeon_device *rdev)
	WREG32(VM_CONTEXT1_CNTL, 0);		WREG32(VM_CONTEXT1_CNTL, 0);
	}		}

	static void evergreen_mc_stop(struct radeon_device rdev, struct evergreen_mc_save save)		void evergreen_mc_stop(struct radeon_device rdev, struct evergreen_mc_save save)
	{		{
	save->vga_control[0] = RREG32(D1VGA_CONTROL);		save->vga_control[0] = RREG32(D1VGA_CONTROL);
	save->vga_control[1] = RREG32(D2VGA_CONTROL);		save->vga_control[1] = RREG32(D2VGA_CONTROL);
	@@ -1011,7 +1011,7 @@ static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_sa
	WREG32(EVERGREEN_D6VGA_CONTROL, 0);		WREG32(EVERGREEN_D6VGA_CONTROL, 0);
	}		}

	static void evergreen_mc_resume(struct radeon_device rdev, struct evergreen_mc_save save)		void evergreen_mc_resume(struct radeon_device rdev, struct evergreen_mc_save save)
	{		{
	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,		WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
	upper_32_bits(rdev->mc.vram_start));		upper_32_bits(rdev->mc.vram_start));
	@@ -1108,7 +1108,7 @@ static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_
	WREG32(VGA_RENDER_CONTROL, save->vga_render_control);		WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
	}		}

	static void evergreen_mc_program(struct radeon_device *rdev)		void evergreen_mc_program(struct radeon_device *rdev)
	{		{
	struct evergreen_mc_save save;		struct evergreen_mc_save save;
	u32 tmp;		u32 tmp;
	@@ -2565,7 +2565,7 @@ void evergreen_irq_disable(struct radeon_device *rdev)
	evergreen_disable_interrupt_state(rdev);		evergreen_disable_interrupt_state(rdev);
	}		}

	static void evergreen_irq_suspend(struct radeon_device *rdev)		void evergreen_irq_suspend(struct radeon_device *rdev)
	{		{
	evergreen_irq_disable(rdev);		evergreen_irq_disable(rdev);
	r600_rlc_stop(rdev);		r600_rlc_stop(rdev);
	@@ -2888,7 +2888,7 @@ static int evergreen_startup(struct radeon_device *rdev)
	return r;		return r;
	}		}
	}		}
	r = btc_mc_load_microcode(rdev);		r = ni_mc_load_microcode(rdev);
	if (r) {		if (r) {
	DRM_ERROR("Failed to load MC firmware!\n");		DRM_ERROR("Failed to load MC firmware!\n");
	return r;		return r;
	@@ -2970,7 +2970,7 @@ int evergreen_resume(struct radeon_device *rdev)

	r = evergreen_startup(rdev);		r = evergreen_startup(rdev);
	if (r) {		if (r) {
	DRM_ERROR("r600 startup failed on resume\n");		DRM_ERROR("evergreen startup failed on resume\n");
	return r;		return r;
	}		}

	@@ -3050,7 +3050,7 @@ int evergreen_init(struct radeon_device *rdev)
	}		}
	/* Must be an ATOMBIOS */		/* Must be an ATOMBIOS */
	if (!rdev->is_atom_bios) {		if (!rdev->is_atom_bios) {
	dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");		dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
	return -EINVAL;		return -EINVAL;
	}		}
	r = radeon_atombios_init(rdev);		r = radeon_atombios_init(rdev);

drivers/gpu/drm/radeon/evergreen_cs.c

+70 −5

Original line number	Original line	Diff line number	Diff line
	@@ -29,6 +29,7 @@
	#include "radeon.h"		#include "radeon.h"
	#include "evergreend.h"		#include "evergreend.h"
	#include "evergreen_reg_safe.h"		#include "evergreen_reg_safe.h"
			#include "cayman_reg_safe.h"

	static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,		static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
	struct radeon_cs_reloc **cs_reloc);		struct radeon_cs_reloc **cs_reloc);
	@@ -425,18 +426,28 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
	{		{
	struct evergreen_cs_track track = (struct evergreen_cs_track )p->track;		struct evergreen_cs_track track = (struct evergreen_cs_track )p->track;
	struct radeon_cs_reloc *reloc;		struct radeon_cs_reloc *reloc;
	u32 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);		u32 last_reg;
	u32 m, i, tmp, *ib;		u32 m, i, tmp, *ib;
	int r;		int r;

			if (p->rdev->family >= CHIP_CAYMAN)
			last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
			else
			last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);

	i = (reg >> 7);		i = (reg >> 7);
	if (i > last_reg) {		if (i > last_reg) {
	dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);		dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
	return -EINVAL;		return -EINVAL;
	}		}
	m = 1 << ((reg >> 2) & 31);		m = 1 << ((reg >> 2) & 31);
			if (p->rdev->family >= CHIP_CAYMAN) {
			if (!(cayman_reg_safe_bm[i] & m))
			return 0;
			} else {
	if (!(evergreen_reg_safe_bm[i] & m))		if (!(evergreen_reg_safe_bm[i] & m))
	return 0;		return 0;
			}
	ib = p->ib->ptr;		ib = p->ib->ptr;
	switch (reg) {		switch (reg) {
	/* force following reg to 0 in an attemp to disable out buffer		/* force following reg to 0 in an attemp to disable out buffer
	@@ -468,12 +479,42 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
	case SQ_VSTMP_RING_ITEMSIZE:		case SQ_VSTMP_RING_ITEMSIZE:
	case VGT_TF_RING_SIZE:		case VGT_TF_RING_SIZE:
	/* get value to populate the IB don't remove */		/* get value to populate the IB don't remove */
	tmp =radeon_get_ib_value(p, idx);		/*tmp =radeon_get_ib_value(p, idx);
	ib[idx] = 0;		ib[idx] = 0;*/
			break;
			case SQ_ESGS_RING_BASE:
			case SQ_GSVS_RING_BASE:
			case SQ_ESTMP_RING_BASE:
			case SQ_GSTMP_RING_BASE:
			case SQ_HSTMP_RING_BASE:
			case SQ_LSTMP_RING_BASE:
			case SQ_PSTMP_RING_BASE:
			case SQ_VSTMP_RING_BASE:
			r = evergreen_cs_packet_next_reloc(p, &reloc);
			if (r) {
			dev_warn(p->dev, "bad SET_CONTEXT_REG "
			"0x%04X\n", reg);
			return -EINVAL;
			}
			ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
	break;		break;
	case DB_DEPTH_CONTROL:		case DB_DEPTH_CONTROL:
	track->db_depth_control = radeon_get_ib_value(p, idx);		track->db_depth_control = radeon_get_ib_value(p, idx);
	break;		break;
			case CAYMAN_DB_EQAA:
			if (p->rdev->family < CHIP_CAYMAN) {
			dev_warn(p->dev, "bad SET_CONTEXT_REG "
			"0x%04X\n", reg);
			return -EINVAL;
			}
			break;
			case CAYMAN_DB_DEPTH_INFO:
			if (p->rdev->family < CHIP_CAYMAN) {
			dev_warn(p->dev, "bad SET_CONTEXT_REG "
			"0x%04X\n", reg);
			return -EINVAL;
			}
			break;
	case DB_Z_INFO:		case DB_Z_INFO:
	r = evergreen_cs_packet_next_reloc(p, &reloc);		r = evergreen_cs_packet_next_reloc(p, &reloc);
	if (r) {		if (r) {
	@@ -559,9 +600,23 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
	track->cb_shader_mask = radeon_get_ib_value(p, idx);		track->cb_shader_mask = radeon_get_ib_value(p, idx);
	break;		break;
	case PA_SC_AA_CONFIG:		case PA_SC_AA_CONFIG:
			if (p->rdev->family >= CHIP_CAYMAN) {
			dev_warn(p->dev, "bad SET_CONTEXT_REG "
			"0x%04X\n", reg);
			return -EINVAL;
			}
	tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;		tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
	track->nsamples = 1 << tmp;		track->nsamples = 1 << tmp;
	break;		break;
			case CAYMAN_PA_SC_AA_CONFIG:
			if (p->rdev->family < CHIP_CAYMAN) {
			dev_warn(p->dev, "bad SET_CONTEXT_REG "
			"0x%04X\n", reg);
			return -EINVAL;
			}
			tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
			track->nsamples = 1 << tmp;
			break;
	case CB_COLOR0_VIEW:		case CB_COLOR0_VIEW:
	case CB_COLOR1_VIEW:		case CB_COLOR1_VIEW:
	case CB_COLOR2_VIEW:		case CB_COLOR2_VIEW:
	@@ -987,6 +1042,16 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
	return -EINVAL;		return -EINVAL;
	}		}
	break;		break;
			case CAYMAN_PACKET3_DEALLOC_STATE:
			if (p->rdev->family < CHIP_CAYMAN) {
			DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
			return -EINVAL;
			}
			if (pkt->count) {
			DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
			return -EINVAL;
			}
			break;
	case PACKET3_INDEX_BASE:		case PACKET3_INDEX_BASE:
	if (pkt->count != 1) {		if (pkt->count != 1) {
	DRM_ERROR("bad INDEX_BASE\n");		DRM_ERROR("bad INDEX_BASE\n");

Original line number	Original line	Diff line number	Diff line
	@@ -36,6 +36,9 @@ $(obj)/r600_reg_safe.h: $(src)/reg_srcs/r600 $(obj)/mkregtable
	$(obj)/evergreen_reg_safe.h: $(src)/reg_srcs/evergreen $(obj)/mkregtable		$(obj)/evergreen_reg_safe.h: $(src)/reg_srcs/evergreen $(obj)/mkregtable
	$(call if_changed,mkregtable)		$(call if_changed,mkregtable)

			$(obj)/cayman_reg_safe.h: $(src)/reg_srcs/cayman $(obj)/mkregtable
			$(call if_changed,mkregtable)

	$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h		$(obj)/r100.o: $(obj)/r100_reg_safe.h $(obj)/rn50_reg_safe.h

	$(obj)/r200.o: $(obj)/r200_reg_safe.h		$(obj)/r200.o: $(obj)/r200_reg_safe.h
	@@ -50,7 +53,7 @@ $(obj)/rs600.o: $(obj)/rs600_reg_safe.h

	$(obj)/r600_cs.o: $(obj)/r600_reg_safe.h		$(obj)/r600_cs.o: $(obj)/r600_reg_safe.h

	$(obj)/evergreen_cs.o: $(obj)/evergreen_reg_safe.h		$(obj)/evergreen_cs.o: $(obj)/evergreen_reg_safe.h $(obj)/cayman_reg_safe.h

	radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \		radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
	radeon_irq.o r300_cmdbuf.o r600_cp.o		radeon_irq.o r300_cmdbuf.o r600_cp.o
	@@ -66,7 +69,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
	r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \		r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
	r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \		r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
	evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \		evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \
	radeon_trace_points.o ni.o		radeon_trace_points.o ni.o cayman_blit_shaders.o

	radeon-$(CONFIG_COMPAT) += radeon_ioc32.o		radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
	radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o		radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

Admin message