drm/i915/display: switch to kernel types

#include "i915_trace.h"

/* Primary plane formats for gen <= 3 */

static const uint32_t i8xx_primary_formats[] = {

static const u32 i8xx_primary_formats[] = {

	DRM_FORMAT_C8,

	DRM_FORMAT_RGB565,

	DRM_FORMAT_XRGB1555,

};

/* Primary plane formats for gen >= 4 */

static const uint32_t i965_primary_formats[] = {

static const u32 i965_primary_formats[] = {

	DRM_FORMAT_C8,

	DRM_FORMAT_RGB565,

	DRM_FORMAT_XRGB8888,

	DRM_FORMAT_XBGR2101010,

};

static const uint64_t i9xx_format_modifiers[] = {

static const u64 i9xx_format_modifiers[] = {

	I915_FORMAT_MOD_X_TILED,

	DRM_FORMAT_MOD_LINEAR,

	DRM_FORMAT_MOD_INVALID

};

/* Cursor formats */

static const uint32_t intel_cursor_formats[] = {

static const u32 intel_cursor_formats[] = {

	DRM_FORMAT_ARGB8888,

};

static const uint64_t cursor_format_modifiers[] = {

static const u64 cursor_format_modifiers[] = {

	DRM_FORMAT_MOD_LINEAR,

	DRM_FORMAT_MOD_INVALID

};

	return clock->dot;

}

static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)

static u32 i9xx_dpll_compute_m(struct dpll *dpll)

{

	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);

}

	clock->p = clock->p1 * clock->p2;

	if (WARN_ON(clock->n == 0 || clock->p == 0))

		return 0;

	clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,

	clock->vco = DIV_ROUND_CLOSEST_ULL((u64)refclk * clock->m,

					   clock->n << 22);

	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);

	struct drm_device *dev = crtc->base.dev;

	unsigned int best_error_ppm;

	struct dpll clock;

	uint64_t m2;

	u64 m2;

	int found = false;

	memset(best_clock, 0, sizeof(*best_clock));

			clock.p = clock.p1 * clock.p2;

			m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *

			m2 = DIV_ROUND_CLOSEST_ULL(((u64)target * clock.p *

					clock.n) << 22, refclk * clock.m1);

			if (m2 > INT_MAX/clock.m1)

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	i915_reg_t reg;

	uint32_t val, pipeconf_val;

	u32 val, pipeconf_val;

	/* Make sure PCH DPLL is enabled */

	assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);

					    enum pipe pipe)

{

	i915_reg_t reg;

	uint32_t val;

	u32 val;

	/* FDI relies on the transcoder */

	assert_fdi_tx_disabled(dev_priv, pipe);

	return 0;

}

static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)

static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)

{

	switch (fb_modifier) {

	case I915_FORMAT_MOD_X_TILED:

	return stride / skl_plane_stride_mult(fb, color_plane, rotation);

}

static u32 skl_plane_ctl_format(uint32_t pixel_format)

static u32 skl_plane_ctl_format(u32 pixel_format)

{

	switch (pixel_format) {

	case DRM_FORMAT_C8:

	}

}

static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)

static u32 skl_plane_ctl_tiling(u64 fb_modifier)

{

	switch (fb_modifier) {

	case DRM_FORMAT_MOD_LINEAR:

static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)

{

	uint32_t temp;

	u32 temp;

	temp = I915_READ(SOUTH_CHICKEN1);

	if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	uint32_t val;

	u32 val;

	val = MBUS_DBOX_A_CREDIT(2);

	val |= MBUS_DBOX_BW_CREDIT(1);

		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));

}

static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)

static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)

{

	uint32_t pixel_rate;

	u32 pixel_rate;

	pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;

	 */

	if (pipe_config->pch_pfit.enabled) {

		uint64_t pipe_w, pipe_h, pfit_w, pfit_h;

		uint32_t pfit_size = pipe_config->pch_pfit.size;

		u64 pipe_w, pipe_h, pfit_w, pfit_h;

		u32 pfit_size = pipe_config->pch_pfit.size;

		pipe_w = pipe_config->pipe_src_w;

		pipe_h = pipe_config->pipe_src_h;

		if (WARN_ON(!pfit_w || !pfit_h))

			return pixel_rate;

		pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,

		pixel_rate = div_u64((u64)pixel_rate * pipe_w * pipe_h,

				     pfit_w * pfit_h);

	}

}

static void

intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)

intel_reduce_m_n_ratio(u32 *num, u32 *den)

{

	while (*num > DATA_LINK_M_N_MASK ||

	       *den > DATA_LINK_M_N_MASK) {

}

static void compute_m_n(unsigned int m, unsigned int n,

			uint32_t *ret_m, uint32_t *ret_n,

			u32 *ret_m, u32 *ret_n,

			bool constant_n)

{

	/*

	else

		*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);

	*ret_m = div_u64((uint64_t) m * *ret_n, n);

	*ret_m = div_u64((u64)m * *ret_n, n);

	intel_reduce_m_n_ratio(ret_m, ret_n);

}

		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);

}

static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)

static u32 pnv_dpll_compute_fp(struct dpll *dpll)

{

	return (1 << dpll->n) << 16 | dpll->m2;

}

static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)

static u32 i9xx_dpll_compute_fp(struct dpll *dpll)

{

	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;

}

	enum pipe pipe = crtc->pipe;

	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;

	uint32_t crtc_vtotal, crtc_vblank_end;

	u32 crtc_vtotal, crtc_vblank_end;

	int vsyncshift = 0;

	/* We need to be careful not to changed the adjusted mode, for otherwise

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;

	uint32_t tmp;

	u32 tmp;

	tmp = I915_READ(HTOTAL(cpu_transcoder));

	pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	uint32_t pipeconf;

	u32 pipeconf;

	pipeconf = 0;

				 struct intel_crtc_state *pipe_config)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	uint32_t tmp;

	u32 tmp;

	if (INTEL_GEN(dev_priv) <= 3 &&

	    (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum intel_display_power_domain power_domain;

	intel_wakeref_t wakeref;

	uint32_t tmp;

	u32 tmp;

	bool ret;

	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);

static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)

{

	uint32_t tmp;

	u32 tmp;

	tmp = I915_READ(SOUTH_CHICKEN2);

	tmp |= FDI_MPHY_IOSFSB_RESET_CTL;

/* WaMPhyProgramming:hsw */

static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)

{

	uint32_t tmp;

	u32 tmp;

	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);

	tmp &= ~(0xFF << 24);

static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,

				 bool with_spread, bool with_fdi)

{

	uint32_t reg, tmp;

	u32 reg, tmp;

	if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))

		with_spread = true;

/* Sequence to disable CLKOUT_DP */

static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)

{

	uint32_t reg, tmp;

	u32 reg, tmp;

	mutex_lock(&dev_priv->sb_lock);

#define BEND_IDX(steps) ((50 + (steps)) / 5)

static const uint16_t sscdivintphase[] = {

static const u16 sscdivintphase[] = {

	[BEND_IDX( 50)] = 0x3B23,

	[BEND_IDX( 45)] = 0x3B23,

	[BEND_IDX( 40)] = 0x3C23,

 */

static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)

{

	uint32_t tmp;

	u32 tmp;

	int idx = BEND_IDX(steps);

	if (WARN_ON(steps % 5 != 0))

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	uint32_t val;

	u32 val;

	val = 0;

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;

	uint32_t ps_ctrl = 0;

	u32 ps_ctrl = 0;

	int id = -1;

	int i;

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	uint32_t tmp;

	u32 tmp;

	tmp = I915_READ(PF_CTL(crtc->pipe));

	struct drm_i915_private *dev_priv = to_i915(dev);

	enum intel_display_power_domain power_domain;

	intel_wakeref_t wakeref;

	uint32_t tmp;

	u32 tmp;

	bool ret;

	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);

	I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");

}

static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)

static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)

{

	if (IS_HASWELL(dev_priv))

		return I915_READ(D_COMP_HSW);

		return I915_READ(D_COMP_BDW);

}

static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)

static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)

{

	if (IS_HASWELL(dev_priv)) {

		mutex_lock(&dev_priv->pcu_lock);

static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,

			      bool switch_to_fclk, bool allow_power_down)

{

	uint32_t val;

	u32 val;

	assert_can_disable_lcpll(dev_priv);

 */

static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)

{

	uint32_t val;

	u32 val;

	val = I915_READ(LCPLL_CTL);

 */

void hsw_enable_pc8(struct drm_i915_private *dev_priv)

{

	uint32_t val;

	u32 val;

	DRM_DEBUG_KMS("Enabling package C8+\n");

void hsw_disable_pc8(struct drm_i915_private *dev_priv)

{

	uint32_t val;

	u32 val;

	DRM_DEBUG_KMS("Disabling package C8+\n");

				struct intel_crtc_state *pipe_config)

{

	enum intel_dpll_id id;

	uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));

	u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));

	switch (ddi_pll_sel) {

	case PORT_CLK_SEL_WRPLL1:

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct intel_shared_dpll *pll;

	enum port port;

	uint32_t tmp;

	u32 tmp;

	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));

			   struct drm_framebuffer *fb,

			   int crtc_x, int crtc_y,

			   unsigned int crtc_w, unsigned int crtc_h,

			   uint32_t src_x, uint32_t src_y,

			   uint32_t src_w, uint32_t src_h,

			   u32 src_x, u32 src_y,

			   u32 src_w, u32 src_h,

			   struct drm_modeset_acquire_ctx *ctx)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->dev);