Commit ba1d18e3 authored by Lionel Landwerlin's avatar Lionel Landwerlin Committed by Chris Wilson
Browse files

drm/i915: capture aux page table error register 



TGL introduced a feature in which we map the main surface to the
auxiliary surface. If we screw up the page tables, the HW has a
register to tell us which engine encounters a fault in the page table
walk.

Signed-off-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
[ickle: Be brave and apply to gen12]
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191025121718.18806-1-lionel.g.landwerlin@intel.com
parent dd5279c7

drivers/gpu/drm/i915/i915_gpu_error.c

+6 −0
Original line number Diff line number Diff line
@@ -734,6 +734,9 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 
	if (IS_GEN_RANGE(m->i915, 8, 11))

		err_printf(m, "GTT_CACHE_EN: 0x%08x\n", error->gtt_cache);



	if (IS_GEN(m->i915, 12))

		err_printf(m, "AUX_ERR_DBG: 0x%08x\n", error->aux_err);



	for (ee = error->engine; ee; ee = ee->next)

		error_print_engine(m, ee, error->capture);
@@ -1554,6 +1557,9 @@ static void capture_reg_state(struct i915_gpu_state *error) 
	if (IS_GEN_RANGE(i915, 8, 11))

		error->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);



	if (IS_GEN(i915, 12))

		error->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);



	/* 4: Everything else */

	if (INTEL_GEN(i915) >= 11) {

		error->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);

drivers/gpu/drm/i915/i915_gpu_error.h

+1 −0
Original line number Diff line number Diff line
@@ -74,6 +74,7 @@ struct i915_gpu_state { 
	u32 gab_ctl;

	u32 gfx_mode;

	u32 gtt_cache;

	u32 aux_err; /* gen12 */



	u32 nfence;

	u64 fence[I915_MAX_NUM_FENCES];

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -2603,6 +2603,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   FAULT_VA_HIGH_BITS		(0xf << 0)

#define   FAULT_GTT_SEL			(1 << 4)



#define GEN12_AUX_ERR_DBG		_MMIO(0x43f4)



#define FPGA_DBG		_MMIO(0x42300)

#define   FPGA_DBG_RM_NOCLAIM	(1 << 31)

CRA Git | Maintained and supported by SUSTech CRA and CCSE