Unverified Commit ba1bc0fc authored Jun 20, 2019 by Petr Cvek Committed by Paul Burton Jun 24, 2019

MIPS: lantiq: Fix bitfield masking

The modification of EXIN register doesn't clean the bitfield before
the writing of a new value. After a few modifications the bitfield would
accumulate only '1's.

Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: hauke@hauke-m.de
Cc: john@phrozen.org
Cc: linux-mips@vger.kernel.org
Cc: openwrt-devel@lists.openwrt.org
Cc: pakahmar@hotmail.com

parent 7c6747bc

arch/mips/lantiq/irq.c

+3 −2

Original line number	Diff line number	Diff line
		@@ -150,8 +150,9 @@ static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
		if (edge)
		irq_set_handler(d->hwirq, handle_edge_irq);

		ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) \|
		(val << (i * 4)), LTQ_EIU_EXIN_C);
		ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) &
		(~(7 << (i * 4)))) \| (val << (i * 4)),
		LTQ_EIU_EXIN_C);
		}
		}

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