Commit ba05173a authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'amlogic-dt64-3' of... 

Merge tag 'amlogic-dt64-3' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt

Another round of 64-bit DT changes for the new Amlogic SoCs.  These
include IR, SPI and ethernet MAC support for the new AXG family SoCs.

* tag 'amlogic-dt64-3' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic

:
  ARM64: dts: meson-axg: enable ethernet for A113D S400 board
  ARM64: dts: meson-axg: add ethernet mac controller
  ARM64: dts: meson-axg: add the SPICC controller
  ARM64: dts: meson-axg: enable IR controller
  arm64: dts: meson-axg: switch uart_ao clock to CLK81
  clk: meson-axg: add clocks dt-bindings required header
  dt-bindings: clock: add compatible variant for the Meson-AXG

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 8c11fcc2 f6f6ac91

Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt

+5 −2
Original line number Diff line number Diff line
@@ -5,8 +5,11 @@ controllers within the SoC. 


Required Properties:



- compatible: should be "amlogic,gxbb-clkc" for GXBB SoC,

	      or "amlogic,gxl-clkc" for GXL and GXM SoC.

- compatible: should be:

		"amlogic,gxbb-clkc" for GXBB SoC,

		"amlogic,gxl-clkc" for GXL and GXM SoC,

		"amlogic,axg-clkc" for AXG SoC.



- reg: physical base address of the clock controller and length of memory

       mapped region.

arch/arm64/boot/dts/amlogic/meson-axg-s400.dts

+13 −0
Original line number Diff line number Diff line
@@ -17,6 +17,19 @@ 
	};

};



&ethmac {

	status = "okay";

	phy-mode = "rgmii";

	pinctrl-0 = <&eth_rgmii_y_pins>;

	pinctrl-names = "default";

};



&uart_AO {

	status = "okay";

};



&ir {

	status = "okay";

	pinctrl-0 = <&remote_input_ao_pins>;

	pinctrl-names = "default";

};

arch/arm64/boot/dts/amlogic/meson-axg.dtsi

+162 −2
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/axg-clkc.h>



/ {

	compatible = "amlogic,meson-axg";
@@ -140,6 +141,28 @@ 
				#reset-cells = <1>;

			};



			spicc0: spi@13000 {

				compatible = "amlogic,meson-axg-spicc";

				reg = <0x0 0x13000 0x0 0x3c>;

				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clkc CLKID_SPICC0>;

				clock-names = "core";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};



			spicc1: spi@15000 {

				compatible = "amlogic,meson-axg-spicc";

				reg = <0x0 0x15000 0x0 0x3c>;

				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clkc CLKID_SPICC1>;

				clock-names = "core";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};



			uart_A: serial@24000 {

				compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";

				reg = <0x0 0x24000 0x0 0x14>;
@@ -155,6 +178,19 @@ 
			};

		};



		ethmac: ethernet@ff3f0000 {

			compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";

			reg = <0x0 0xff3f0000 0x0 0x10000

				0x0 0xff634540 0x0 0x8>;

			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "macirq";

			clocks = <&clkc CLKID_ETH>,

				 <&clkc CLKID_FCLK_DIV2>,

				 <&clkc CLKID_MPLL2>;

			clock-names = "stmmaceth", "clkin0", "clkin1";

			status = "disabled";

		};



		gic: interrupt-controller@ffc01000 {

			compatible = "arm,gic-400";

			reg = <0x0 0xffc01000 0 0x1000>,
@@ -215,6 +251,46 @@ 
					gpio-ranges = <&pinctrl_periphs 0 0 86>;

				};



				eth_rgmii_x_pins: eth-x-rgmii {

					mux {

						groups = "eth_mdio_x",

						       "eth_mdc_x",

						       "eth_rgmii_rx_clk_x",

						       "eth_rx_dv_x",

						       "eth_rxd0_x",

						       "eth_rxd1_x",

						       "eth_rxd2_rgmii",

						       "eth_rxd3_rgmii",

						       "eth_rgmii_tx_clk",

						       "eth_txen_x",

						       "eth_txd0_x",

						       "eth_txd1_x",

						       "eth_txd2_rgmii",

						       "eth_txd3_rgmii";

						function = "eth";

					};

				};



				eth_rgmii_y_pins: eth-y-rgmii {

					mux {

						groups = "eth_mdio_y",

						       "eth_mdc_y",

						       "eth_rgmii_rx_clk_y",

						       "eth_rx_dv_y",

						       "eth_rxd0_y",

						       "eth_rxd1_y",

						       "eth_rxd2_rgmii",

						       "eth_rxd3_rgmii",

						       "eth_rgmii_tx_clk",

						       "eth_txen_y",

						       "eth_txd0_y",

						       "eth_txd1_y",

						       "eth_txd2_rgmii",

						       "eth_txd3_rgmii";

						function = "eth";

					};

				};



				pwm_a_a_pins: pwm_a_a {

					mux {

						groups = "pwm_a_a";
@@ -298,6 +374,76 @@ 
						function = "pwm_d";

					};

				};



				spi0_pins: spi0 {

					mux {

						groups = "spi0_miso",

							"spi0_mosi",

							"spi0_clk";

						function = "spi0";

					};

				};



				spi0_ss0_pins: spi0_ss0 {

					mux {

						groups = "spi0_ss0";

						function = "spi0";

					};

				};



				spi0_ss1_pins: spi0_ss1 {

					mux {

						groups = "spi0_ss1";

						function = "spi0";

					};

				};



				spi0_ss2_pins: spi0_ss2 {

					mux {

						groups = "spi0_ss2";

						function = "spi0";

					};

				};





				spi1_a_pins: spi1_a {

					mux {

						groups = "spi1_miso_a",

							"spi1_mosi_a",

							"spi1_clk_a";

						function = "spi1";

					};

				};



				spi1_ss0_a_pins: spi1_ss0_a {

					mux {

						groups = "spi1_ss0_a";

						function = "spi1";

					};

				};



				spi1_ss1_pins: spi1_ss1 {

					mux {

						groups = "spi1_ss1";

						function = "spi1";

					};

				};



				spi1_x_pins: spi1_x {

					mux {

						groups = "spi1_miso_x",

							"spi1_mosi_x",

							"spi1_clk_x";

						function = "spi1";

					};

				};



				spi1_ss0_x_pins: spi1_ss0_x {

					mux {

						groups = "spi1_ss0_x";

						function = "spi1";

					};

				};

			};

		};
@@ -341,6 +487,13 @@ 
					#gpio-cells = <2>;

					gpio-ranges = <&pinctrl_aobus 0 0 15>;

				};



				remote_input_ao_pins: remote_input_ao {

					mux {

						groups = "remote_input_ao";

						function = "remote_input_ao";

					};

				};

			};



			pwm_AO_ab: pwm@7000 {
@@ -361,7 +514,7 @@ 
				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";

				reg = <0x0 0x3000 0x0 0x18>;

				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;

				clocks = <&xtal>, <&xtal>, <&xtal>;

				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;

				clock-names = "xtal", "pclk", "baud";

				status = "disabled";

			};
@@ -370,10 +523,17 @@ 
				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";

				reg = <0x0 0x4000 0x0 0x18>;

				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;

				clocks = <&xtal>, <&xtal>, <&xtal>;

				clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;

				clock-names = "xtal", "pclk", "baud";

				status = "disabled";

			};



			ir: ir@8000 {

				compatible = "amlogic,meson-gxbb-ir";

				reg = <0x0 0x8000 0x0 0x20>;

				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;

				status = "disabled";

			};

		};

	};

};

include/dt-bindings/clock/axg-clkc.h

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+71 −0
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */

/*

 * Meson-AXG clock tree IDs

 *

 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.

 */



#ifndef __AXG_CLKC_H

#define __AXG_CLKC_H



#define CLKID_SYS_PLL				0

#define CLKID_FIXED_PLL				1

#define CLKID_FCLK_DIV2				2

#define CLKID_FCLK_DIV3				3

#define CLKID_FCLK_DIV4				4

#define CLKID_FCLK_DIV5				5

#define CLKID_FCLK_DIV7				6

#define CLKID_GP0_PLL				7

#define CLKID_CLK81				10

#define CLKID_MPLL0				11

#define CLKID_MPLL1				12

#define CLKID_MPLL2				13

#define CLKID_MPLL3				14

#define CLKID_DDR				15

#define CLKID_AUDIO_LOCKER			16

#define CLKID_MIPI_DSI_HOST			17

#define CLKID_ISA				18

#define CLKID_PL301				19

#define CLKID_PERIPHS				20

#define CLKID_SPICC0				21

#define CLKID_I2C				22

#define CLKID_RNG0				23

#define CLKID_UART0				24

#define CLKID_MIPI_DSI_PHY			25

#define CLKID_SPICC1				26

#define CLKID_PCIE_A				27

#define CLKID_PCIE_B				28

#define CLKID_HIU_IFACE				29

#define CLKID_ASSIST_MISC			30

#define CLKID_SD_EMMC_B				31

#define CLKID_SD_EMMC_C				32

#define CLKID_DMA				33

#define CLKID_SPI				34

#define CLKID_AUDIO				35

#define CLKID_ETH				36

#define CLKID_UART1				37

#define CLKID_G2D				38

#define CLKID_USB0				39

#define CLKID_USB1				40

#define CLKID_RESET				41

#define CLKID_USB				42

#define CLKID_AHB_ARB0				43

#define CLKID_EFUSE				44

#define CLKID_BOOT_ROM				45

#define CLKID_AHB_DATA_BUS			46

#define CLKID_AHB_CTRL_BUS			47

#define CLKID_USB1_DDR_BRIDGE			48

#define CLKID_USB0_DDR_BRIDGE			49

#define CLKID_MMC_PCLK				50

#define CLKID_VPU_INTR				51

#define CLKID_SEC_AHB_AHB3_BRIDGE		52

#define CLKID_GIC				53

#define CLKID_AO_MEDIA_CPU			54

#define CLKID_AO_AHB_SRAM			55

#define CLKID_AO_AHB_BUS			56

#define CLKID_AO_IFACE				57

#define CLKID_AO_I2C				58

#define CLKID_SD_EMMC_B_CLK0			59

#define CLKID_SD_EMMC_C_CLK0			60



#endif /* __AXG_CLKC_H */

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