Commit ba0411dd authored Jul 10, 2019 by Sai Prakash Ranjan Committed by Bjorn Andersson Aug 05, 2019

arm64: dts: sdm845: Add device node for Last level cache controller



Last level cache (aka. system cache) controller provides control
over the last level cache present on SDM845. This cache lies after
the memory noc, right before the DDR.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

parent 887e5421

arch/arm64/boot/dts/qcom/sdm845.dtsi

+7 −0

Original line number	Diff line number	Diff line
		@@ -1275,6 +1275,13 @@
		};
		};

		cache-controller@1100000 {
		compatible = "qcom,sdm845-llcc";
		reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
		reg-names = "llcc_base", "llcc_broadcast_base";
		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
		};

		ufs_mem_hc: ufshc@1d84000 {
		compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
		"jedec,ufs-2.0";

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