Commit b9e24d30 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge Rockchip pmdomain fix into next/defconfig 

Commit e330eb86 ("ARM: multi_v7_defconfig: enable Rockchip io-domain
driver") turns on a driver that was broken on 4.4-rc3 and fixed in 4.4-rc4.

This backmerges in the bugfix from mainline to keep the defconfig branch
testable by itself.

* commit 'd7b53fd9':
  drm/rockchip: vop: Correct enabled clocks during setup
  drm/i915: Don't override output type for DDI HDMI
  drm/i915: Don't compare has_drrs strictly in pipe config
  drm/i915: Mark uneven memory banks on gen4 desktop as unknown swizzling
parents 954e953c d7b53fd9

drivers/gpu/drm/i915/i915_gem_fence.c

+27 −9
Original line number Diff line number Diff line
@@ -642,11 +642,10 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) 
		}



		/* check for L-shaped memory aka modified enhanced addressing */

		if (IS_GEN4(dev)) {

			uint32_t ddc2 = I915_READ(DCC2);



			if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE))

				dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;

		if (IS_GEN4(dev) &&

		    !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {

			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;

			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;

		}



		if (dcc == 0xffffffff) {
@@ -675,16 +674,35 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) 
		 * matching, which was the case for the swizzling required in

		 * the table above, or from the 1-ch value being less than

		 * the minimum size of a rank.

		 *

		 * Reports indicate that the swizzling actually

		 * varies depending upon page placement inside the

		 * channels, i.e. we see swizzled pages where the

		 * banks of memory are paired and unswizzled on the

		 * uneven portion, so leave that as unknown.

		 */

		if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {

			swizzle_x = I915_BIT_6_SWIZZLE_NONE;

			swizzle_y = I915_BIT_6_SWIZZLE_NONE;

		} else {

		if (I915_READ16(C0DRB3) == I915_READ16(C1DRB3)) {

			swizzle_x = I915_BIT_6_SWIZZLE_9_10;

			swizzle_y = I915_BIT_6_SWIZZLE_9;

		}

	}



	if (swizzle_x == I915_BIT_6_SWIZZLE_UNKNOWN ||

	    swizzle_y == I915_BIT_6_SWIZZLE_UNKNOWN) {

		/* Userspace likes to explode if it sees unknown swizzling,

		 * so lie. We will finish the lie when reporting through

		 * the get-tiling-ioctl by reporting the physical swizzle

		 * mode as unknown instead.

		 *

		 * As we don't strictly know what the swizzling is, it may be

		 * bit17 dependent, and so we need to also prevent the pages

		 * from being moved.

		 */

		dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;

		swizzle_x = I915_BIT_6_SWIZZLE_NONE;

		swizzle_y = I915_BIT_6_SWIZZLE_NONE;

	}



	dev_priv->mm.bit_6_swizzle_x = swizzle_x;

	dev_priv->mm.bit_6_swizzle_y = swizzle_y;

}

drivers/gpu/drm/i915/intel_display.c

+0 −1
Original line number Diff line number Diff line
@@ -12460,7 +12460,6 @@ intel_pipe_config_compare(struct drm_device *dev, 
	if (INTEL_INFO(dev)->gen < 8) {

		PIPE_CONF_CHECK_M_N(dp_m_n);



		PIPE_CONF_CHECK_I(has_drrs);

		if (current_config->has_drrs)

			PIPE_CONF_CHECK_M_N(dp_m2_n2);

	} else

drivers/gpu/drm/i915/intel_dp.c

+2 −1
Original line number Diff line number Diff line
@@ -5153,7 +5153,8 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) 
	enum intel_display_power_domain power_domain;

	enum irqreturn ret = IRQ_NONE;



	if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)

	if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&

	    intel_dig_port->base.type != INTEL_OUTPUT_HDMI)

		intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;



	if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

+14 −22
Original line number Diff line number Diff line
@@ -1575,32 +1575,25 @@ static int vop_initial(struct vop *vop) 
		return PTR_ERR(vop->dclk);

	}



	ret = clk_prepare(vop->hclk);

	if (ret < 0) {

		dev_err(vop->dev, "failed to prepare hclk\n");

		return ret;

	}



	ret = clk_prepare(vop->dclk);

	if (ret < 0) {

		dev_err(vop->dev, "failed to prepare dclk\n");

		goto err_unprepare_hclk;

		return ret;

	}



	ret = clk_prepare(vop->aclk);

	/* Enable both the hclk and aclk to setup the vop */

	ret = clk_prepare_enable(vop->hclk);

	if (ret < 0) {

		dev_err(vop->dev, "failed to prepare aclk\n");

		dev_err(vop->dev, "failed to prepare/enable hclk\n");

		goto err_unprepare_dclk;

	}



	/*

	 * enable hclk, so that we can config vop register.

	 */

	ret = clk_enable(vop->hclk);

	ret = clk_prepare_enable(vop->aclk);

	if (ret < 0) {

		dev_err(vop->dev, "failed to prepare aclk\n");

		goto err_unprepare_aclk;

		dev_err(vop->dev, "failed to prepare/enable aclk\n");

		goto err_disable_hclk;

	}



	/*

	 * do hclk_reset, reset all vop registers.

	 */
@@ -1608,7 +1601,7 @@ static int vop_initial(struct vop *vop) 
	if (IS_ERR(ahb_rst)) {

		dev_err(vop->dev, "failed to get ahb reset\n");

		ret = PTR_ERR(ahb_rst);

		goto err_disable_hclk;

		goto err_disable_aclk;

	}

	reset_control_assert(ahb_rst);

	usleep_range(10, 20);
@@ -1634,26 +1627,25 @@ static int vop_initial(struct vop *vop) 
	if (IS_ERR(vop->dclk_rst)) {

		dev_err(vop->dev, "failed to get dclk reset\n");

		ret = PTR_ERR(vop->dclk_rst);

		goto err_unprepare_aclk;

		goto err_disable_aclk;

	}

	reset_control_assert(vop->dclk_rst);

	usleep_range(10, 20);

	reset_control_deassert(vop->dclk_rst);



	clk_disable(vop->hclk);

	clk_disable(vop->aclk);



	vop->is_enabled = false;



	return 0;



err_disable_aclk:

	clk_disable_unprepare(vop->aclk);

err_disable_hclk:

	clk_disable(vop->hclk);

err_unprepare_aclk:

	clk_unprepare(vop->aclk);

	clk_disable_unprepare(vop->hclk);

err_unprepare_dclk:

	clk_unprepare(vop->dclk);

err_unprepare_hclk:

	clk_unprepare(vop->hclk);

	return ret;

}

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