Commit b9cdbe6e authored by Lorenzo Pieralisi's avatar Lorenzo Pieralisi Committed by Bjorn Helgaas
Browse files

ARM: Implement pci_remap_cfgspace() interface 



The PCI bus specification (rev 3.0, 3.2.5 "Transaction Ordering and
Posting") defines rules for PCI configuration space transactions ordering
and posting, that state that configuration writes have to be non-posted
transactions.

Current ioremap interface on ARM provides mapping functions that provide
"bufferable" writes transactions (ie ioremap uses MT_DEVICE memory type)
aka posted writes, so PCI host controller drivers have no arch interface to
remap PCI configuration space with memory attributes that comply with the
PCI specifications for configuration space.

Implement an ARM specific pci_remap_cfgspace() interface that allows to map
PCI config memory regions with MT_UNCACHED memory type (ie strongly ordered
- non-posted writes), providing a remap function that complies with PCI
specifications for config space transactions.

Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@armlinux.org.uk>
parent f1e209b7

arch/arm/include/asm/io.h

+10 −0
Original line number Diff line number Diff line
@@ -186,6 +186,16 @@ static inline void pci_ioremap_set_mem_type(int mem_type) {} 


extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);



/*

 * PCI configuration space mapping function.

 *

 * The PCI specification does not allow configuration write

 * transactions to be posted. Add an arch specific

 * pci_remap_cfgspace() definition that is implemented

 * through strongly ordered memory mappings.

 */

#define pci_remap_cfgspace pci_remap_cfgspace

void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size);

/*

 * Now, pick up the machine-defined IO definitions

 */

arch/arm/mm/ioremap.c

+7 −0
Original line number Diff line number Diff line
@@ -481,6 +481,13 @@ int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr) 
				  __pgprot(get_mem_type(pci_ioremap_mem_type)->prot_pte));

}

EXPORT_SYMBOL_GPL(pci_ioremap_io);



void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size)

{

	return arch_ioremap_caller(res_cookie, size, MT_UNCACHED,

				   __builtin_return_address(0));

}

EXPORT_SYMBOL_GPL(pci_remap_cfgspace);

#endif



/*

arch/arm/mm/nommu.c

+12 −0
Original line number Diff line number Diff line
@@ -433,6 +433,18 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size) 
}

EXPORT_SYMBOL(ioremap_wc);



#ifdef CONFIG_PCI



#include <asm/mach/map.h>



void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size)

{

	return arch_ioremap_caller(res_cookie, size, MT_UNCACHED,

				   __builtin_return_address(0));

}

EXPORT_SYMBOL_GPL(pci_remap_cfgspace);

#endif



void *arch_memremap_wb(phys_addr_t phys_addr, size_t size)

{

	return (void *)phys_addr;

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