Commit b99afae1 authored by Nicolas Pitre's avatar Nicolas Pitre Committed by Russell King
Browse files

ARM: 8805/2: remove unneeded naked function usage 



The naked attribute is known to confuse some old gcc versions when
function arguments aren't explicitly listed as inline assembly operands
despite the gcc documentation. That resulted in commit 9a40ac86
("ARM: 6164/1: Add kto and kfrom to input operands list.").

Yet that commit has problems of its own by having assembly operand
constraints completely wrong. If the generated code has been OK since
then, it is due to luck rather than correctness. So this patch also
provides proper assembly operand constraints, and removes two instances
of redundant register usages in the implementation while at it.

Inspection of the generated code with this patch doesn't show any
obvious quality degradation either, so not relying on __naked at all
will make the code less fragile, and avoid some issues with clang.

The only remaining __naked instances (excluding the kprobes test cases)
are exynos_pm_power_up_setup(), tc2_pm_power_up_setup() and

cci_enable_port_for_self(. But in the first two cases, only the function
address is used by the compiler with no chance of inlining it by
mistake, and the third case is called from assembly code only. And the
fact that no stack is available when the corresponding code is executed
does warrant the __naked usage in those cases.

Signed-off-by: default avatarNicolas Pitre <nico@linaro.org>
Reviewed-by: default avatarStefan Agner <stefan@agner.ch>
Tested-by: default avatarStefan Agner <stefan@agner.ch>
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent 31d0b9f9

arch/arm/mm/copypage-fa.c

+17 −18
Original line number Diff line number Diff line
@@ -17,26 +17,25 @@ 
/*

 * Faraday optimised copy_user_page

 */

static void __naked

fa_copy_user_page(void *kto, const void *kfrom)

static void fa_copy_user_page(void *kto, const void *kfrom)

{

	asm("\

	stmfd	sp!, {r4, lr}			@ 2\n\

	mov	r2, %0				@ 1\n\

1:	ldmia	r1!, {r3, r4, ip, lr}		@ 4\n\

	stmia	r0, {r3, r4, ip, lr}		@ 4\n\

	mcr	p15, 0, r0, c7, c14, 1		@ 1   clean and invalidate D line\n\

	add	r0, r0, #16			@ 1\n\

	ldmia	r1!, {r3, r4, ip, lr}		@ 4\n\

	stmia	r0, {r3, r4, ip, lr}		@ 4\n\

	mcr	p15, 0, r0, c7, c14, 1		@ 1   clean and invalidate D line\n\

	add	r0, r0, #16			@ 1\n\

	subs	r2, r2, #1			@ 1\n\

	int tmp;



	asm volatile ("\

1:	ldmia	%1!, {r3, r4, ip, lr}		@ 4\n\

	stmia	%0, {r3, r4, ip, lr}		@ 4\n\

	mcr	p15, 0, %0, c7, c14, 1		@ 1   clean and invalidate D line\n\

	add	%0, %0, #16			@ 1\n\

	ldmia	%1!, {r3, r4, ip, lr}		@ 4\n\

	stmia	%0, {r3, r4, ip, lr}		@ 4\n\

	mcr	p15, 0, %0, c7, c14, 1		@ 1   clean and invalidate D line\n\

	add	%0, %0, #16			@ 1\n\

	subs	%2, %2, #1			@ 1\n\

	bne	1b				@ 1\n\

	mcr	p15, 0, r2, c7, c10, 4		@ 1   drain WB\n\

	ldmfd	sp!, {r4, pc}			@ 3"

	:

	: "I" (PAGE_SIZE / 32));

	mcr	p15, 0, %2, c7, c10, 4		@ 1   drain WB"

	: "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)

	: "2" (PAGE_SIZE / 32)

	: "r3", "r4", "ip", "lr");

}



void fa_copy_user_highpage(struct page *to, struct page *from,

arch/arm/mm/copypage-feroceon.c

+48 −50
Original line number Diff line number Diff line
@@ -13,58 +13,56 @@ 
#include <linux/init.h>

#include <linux/highmem.h>



static void __naked

feroceon_copy_user_page(void *kto, const void *kfrom)

static void feroceon_copy_user_page(void *kto, const void *kfrom)

{

	asm("\

	stmfd	sp!, {r4-r9, lr}		\n\

	mov	ip, %2				\n\

1:	mov	lr, r1				\n\

	ldmia	r1!, {r2 - r9}			\n\

	pld	[lr, #32]			\n\

	pld	[lr, #64]			\n\

	pld	[lr, #96]			\n\

	pld	[lr, #128]			\n\

	pld	[lr, #160]			\n\

	pld	[lr, #192]			\n\

	pld	[lr, #224]			\n\

	stmia	r0, {r2 - r9}			\n\

	ldmia	r1!, {r2 - r9}			\n\

	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D line\n\

	add	r0, r0, #32			\n\

	stmia	r0, {r2 - r9}			\n\

	ldmia	r1!, {r2 - r9}			\n\

	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D line\n\

	add	r0, r0, #32			\n\

	stmia	r0, {r2 - r9}			\n\

	ldmia	r1!, {r2 - r9}			\n\

	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D line\n\

	add	r0, r0, #32			\n\

	stmia	r0, {r2 - r9}			\n\

	ldmia	r1!, {r2 - r9}			\n\

	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D line\n\

	add	r0, r0, #32			\n\

	stmia	r0, {r2 - r9}			\n\

	ldmia	r1!, {r2 - r9}			\n\

	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D line\n\

	add	r0, r0, #32			\n\

	stmia	r0, {r2 - r9}			\n\

	ldmia	r1!, {r2 - r9}			\n\

	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D line\n\

	add	r0, r0, #32			\n\

	stmia	r0, {r2 - r9}			\n\

	ldmia	r1!, {r2 - r9}			\n\

	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D line\n\

	add	r0, r0, #32			\n\

	stmia	r0, {r2 - r9}			\n\

	subs	ip, ip, #(32 * 8)		\n\

	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D line\n\

	add	r0, r0, #32			\n\

	int tmp;



	asm volatile ("\

1:	ldmia	%1!, {r2 - r7, ip, lr}		\n\

	pld	[%1, #0]			\n\

	pld	[%1, #32]			\n\

	pld	[%1, #64]			\n\

	pld	[%1, #96]			\n\

	pld	[%1, #128]			\n\

	pld	[%1, #160]			\n\

	pld	[%1, #192]			\n\

	stmia	%0, {r2 - r7, ip, lr}		\n\

	ldmia	%1!, {r2 - r7, ip, lr}		\n\

	mcr	p15, 0, %0, c7, c14, 1		@ clean and invalidate D line\n\

	add	%0, %0, #32			\n\

	stmia	%0, {r2 - r7, ip, lr}		\n\

	ldmia	%1!, {r2 - r7, ip, lr}		\n\

	mcr	p15, 0, %0, c7, c14, 1		@ clean and invalidate D line\n\

	add	%0, %0, #32			\n\

	stmia	%0, {r2 - r7, ip, lr}		\n\

	ldmia	%1!, {r2 - r7, ip, lr}		\n\

	mcr	p15, 0, %0, c7, c14, 1		@ clean and invalidate D line\n\

	add	%0, %0, #32			\n\

	stmia	%0, {r2 - r7, ip, lr}		\n\

	ldmia	%1!, {r2 - r7, ip, lr}		\n\

	mcr	p15, 0, %0, c7, c14, 1		@ clean and invalidate D line\n\

	add	%0, %0, #32			\n\

	stmia	%0, {r2 - r7, ip, lr}		\n\

	ldmia	%1!, {r2 - r7, ip, lr}		\n\

	mcr	p15, 0, %0, c7, c14, 1		@ clean and invalidate D line\n\

	add	%0, %0, #32			\n\

	stmia	%0, {r2 - r7, ip, lr}		\n\

	ldmia	%1!, {r2 - r7, ip, lr}		\n\

	mcr	p15, 0, %0, c7, c14, 1		@ clean and invalidate D line\n\

	add	%0, %0, #32			\n\

	stmia	%0, {r2 - r7, ip, lr}		\n\

	ldmia	%1!, {r2 - r7, ip, lr}		\n\

	mcr	p15, 0, %0, c7, c14, 1		@ clean and invalidate D line\n\

	add	%0, %0, #32			\n\

	stmia	%0, {r2 - r7, ip, lr}		\n\

	subs	%2, %2, #(32 * 8)		\n\

	mcr	p15, 0, %0, c7, c14, 1		@ clean and invalidate D line\n\

	add	%0, %0, #32			\n\

	bne	1b				\n\

	mcr	p15, 0, ip, c7, c10, 4		@ drain WB\n\

	ldmfd	sp!, {r4-r9, pc}"

	:

	: "r" (kto), "r" (kfrom), "I" (PAGE_SIZE));

	mcr	p15, 0, %2, c7, c10, 4		@ drain WB"

	: "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)

	: "2" (PAGE_SIZE)

	: "r2", "r3", "r4", "r5", "r6", "r7", "ip", "lr");

}



void feroceon_copy_user_highpage(struct page *to, struct page *from,

arch/arm/mm/copypage-v4mc.c

+9 −10
Original line number Diff line number Diff line
@@ -40,12 +40,11 @@ static DEFINE_RAW_SPINLOCK(minicache_lock); 
 * instruction.  If your processor does not supply this, you have to write your

 * own copy_user_highpage that does the right thing.

 */

static void __naked

mc_copy_user_page(void *from, void *to)

static void mc_copy_user_page(void *from, void *to)

{

	asm volatile(

	"stmfd	sp!, {r4, lr}			@ 2\n\

	mov	r4, %2				@ 1\n\

	int tmp;



	asm volatile ("\

	ldmia	%0!, {r2, r3, ip, lr}		@ 4\n\

1:	mcr	p15, 0, %1, c7, c6, 1		@ 1   invalidate D line\n\

	stmia	%1!, {r2, r3, ip, lr}		@ 4\n\
@@ -55,13 +54,13 @@ mc_copy_user_page(void *from, void *to) 
	mcr	p15, 0, %1, c7, c6, 1		@ 1   invalidate D line\n\

	stmia	%1!, {r2, r3, ip, lr}		@ 4\n\

	ldmia	%0!, {r2, r3, ip, lr}		@ 4\n\

	subs	r4, r4, #1			@ 1\n\

	subs	%2, %2, #1			@ 1\n\

	stmia	%1!, {r2, r3, ip, lr}		@ 4\n\

	ldmneia	%0!, {r2, r3, ip, lr}		@ 4\n\

	bne	1b				@ 1\n\

	ldmfd	sp!, {r4, pc}			@ 3"

	:

	: "r" (from), "r" (to), "I" (PAGE_SIZE / 64));

	bne	1b				@ "

	: "+&r" (from), "+&r" (to), "=&r" (tmp)

	: "2" (PAGE_SIZE / 64)

	: "r2", "r3", "ip", "lr");

}



void v4_mc_copy_user_highpage(struct page *to, struct page *from,

arch/arm/mm/copypage-v4wb.c

+20 −21
Original line number Diff line number Diff line
@@ -22,29 +22,28 @@ 
 * instruction.  If your processor does not supply this, you have to write your

 * own copy_user_highpage that does the right thing.

 */

static void __naked

v4wb_copy_user_page(void *kto, const void *kfrom)

static void v4wb_copy_user_page(void *kto, const void *kfrom)

{

	asm("\

	stmfd	sp!, {r4, lr}			@ 2\n\

	mov	r2, %2				@ 1\n\

	ldmia	r1!, {r3, r4, ip, lr}		@ 4\n\

1:	mcr	p15, 0, r0, c7, c6, 1		@ 1   invalidate D line\n\

	stmia	r0!, {r3, r4, ip, lr}		@ 4\n\

	ldmia	r1!, {r3, r4, ip, lr}		@ 4+1\n\

	stmia	r0!, {r3, r4, ip, lr}		@ 4\n\

	ldmia	r1!, {r3, r4, ip, lr}		@ 4\n\

	mcr	p15, 0, r0, c7, c6, 1		@ 1   invalidate D line\n\

	stmia	r0!, {r3, r4, ip, lr}		@ 4\n\

	ldmia	r1!, {r3, r4, ip, lr}		@ 4\n\

	subs	r2, r2, #1			@ 1\n\

	stmia	r0!, {r3, r4, ip, lr}		@ 4\n\

	ldmneia	r1!, {r3, r4, ip, lr}		@ 4\n\

	int tmp;



	asm volatile ("\

	ldmia	%1!, {r3, r4, ip, lr}		@ 4\n\

1:	mcr	p15, 0, %0, c7, c6, 1		@ 1   invalidate D line\n\

	stmia	%0!, {r3, r4, ip, lr}		@ 4\n\

	ldmia	%1!, {r3, r4, ip, lr}		@ 4+1\n\

	stmia	%0!, {r3, r4, ip, lr}		@ 4\n\

	ldmia	%1!, {r3, r4, ip, lr}		@ 4\n\

	mcr	p15, 0, %0, c7, c6, 1		@ 1   invalidate D line\n\

	stmia	%0!, {r3, r4, ip, lr}		@ 4\n\

	ldmia	%1!, {r3, r4, ip, lr}		@ 4\n\

	subs	%2, %2, #1			@ 1\n\

	stmia	%0!, {r3, r4, ip, lr}		@ 4\n\

	ldmneia	%1!, {r3, r4, ip, lr}		@ 4\n\

	bne	1b				@ 1\n\

	mcr	p15, 0, r1, c7, c10, 4		@ 1   drain WB\n\

	ldmfd	 sp!, {r4, pc}			@ 3"

	:

	: "r" (kto), "r" (kfrom), "I" (PAGE_SIZE / 64));

	mcr	p15, 0, %1, c7, c10, 4		@ 1   drain WB"

	: "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)

	: "2" (PAGE_SIZE / 64)

	: "r3", "r4", "ip", "lr");

}



void v4wb_copy_user_highpage(struct page *to, struct page *from,

arch/arm/mm/copypage-v4wt.c

+18 −19
Original line number Diff line number Diff line
@@ -20,27 +20,26 @@ 
 * dirty data in the cache.  However, we do have to ensure that

 * subsequent reads are up to date.

 */

static void __naked

v4wt_copy_user_page(void *kto, const void *kfrom)

static void v4wt_copy_user_page(void *kto, const void *kfrom)

{

	asm("\

	stmfd	sp!, {r4, lr}			@ 2\n\

	mov	r2, %2				@ 1\n\

	ldmia	r1!, {r3, r4, ip, lr}		@ 4\n\

1:	stmia	r0!, {r3, r4, ip, lr}		@ 4\n\

	ldmia	r1!, {r3, r4, ip, lr}		@ 4+1\n\

	stmia	r0!, {r3, r4, ip, lr}		@ 4\n\

	ldmia	r1!, {r3, r4, ip, lr}		@ 4\n\

	stmia	r0!, {r3, r4, ip, lr}		@ 4\n\

	ldmia	r1!, {r3, r4, ip, lr}		@ 4\n\

	subs	r2, r2, #1			@ 1\n\

	stmia	r0!, {r3, r4, ip, lr}		@ 4\n\

	ldmneia	r1!, {r3, r4, ip, lr}		@ 4\n\

	int tmp;



	asm volatile ("\

	ldmia	%1!, {r3, r4, ip, lr}		@ 4\n\

1:	stmia	%0!, {r3, r4, ip, lr}		@ 4\n\

	ldmia	%1!, {r3, r4, ip, lr}		@ 4+1\n\

	stmia	%0!, {r3, r4, ip, lr}		@ 4\n\

	ldmia	%1!, {r3, r4, ip, lr}		@ 4\n\

	stmia	%0!, {r3, r4, ip, lr}		@ 4\n\

	ldmia	%1!, {r3, r4, ip, lr}		@ 4\n\

	subs	%2, %2, #1			@ 1\n\

	stmia	%0!, {r3, r4, ip, lr}		@ 4\n\

	ldmneia	%1!, {r3, r4, ip, lr}		@ 4\n\

	bne	1b				@ 1\n\

	mcr	p15, 0, r2, c7, c7, 0		@ flush ID cache\n\

	ldmfd	sp!, {r4, pc}			@ 3"

	:

	: "r" (kto), "r" (kfrom), "I" (PAGE_SIZE / 64));

	mcr	p15, 0, %2, c7, c7, 0		@ flush ID cache"

	: "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)

	: "2" (PAGE_SIZE / 64)

	: "r3", "r4", "ip", "lr");

}



void v4wt_copy_user_highpage(struct page *to, struct page *from,

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