Commit b98ac05d authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by Josh Boyer
Browse files

[POWERPC] 4xx: Deal with 44x virtually tagged icache 



The 44x family has an interesting "feature" which is a virtually
tagged instruction cache (yuck !). So far, we haven't dealt with
it properly, which means we've been mostly lucky or people didn't
report the problems, unless people have been running custom patches
in their distro...

This is an attempt at fixing it properly. I chose to do it by
setting a global flag whenever we change a PTE that was previously
marked executable, and flush the entire instruction cache upon
return to user space when that happens.

This is a bit heavy handed, but it's hard to do more fine grained
flushes as the icbi instruction, on those processor, for some very
strange reasons (since the cache is virtually mapped) still requires
a valid TLB entry for reading in the target address space, which
isn't something I want to deal with.

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarJosh Boyer <jwboyer@linux.vnet.ibm.com>
parent e701d269

arch/powerpc/kernel/entry_32.S

+23 −0
Original line number Diff line number Diff line
@@ -244,6 +244,13 @@ syscall_exit_cont: 
	andis.	r10,r0,DBCR0_IC@h

	bnel-	load_dbcr0

#endif

#ifdef CONFIG_44x

	lis	r4,icache_44x_need_flush@ha

	lwz	r5,icache_44x_need_flush@l(r4)

	cmplwi	cr0,r5,0

	bne-	2f

1:

#endif /* CONFIG_44x */

	stwcx.	r0,0,r1			/* to clear the reservation */

	lwz	r4,_LINK(r1)

	lwz	r5,_CCR(r1)
@@ -258,6 +265,12 @@ syscall_exit_cont: 
	mtspr	SPRN_SRR1,r8

	SYNC

	RFI

#ifdef CONFIG_44x

2:	li	r7,0

	iccci	r0,r0

	stw	r7,icache_44x_need_flush@l(r4)

	b	1b

#endif  /* CONFIG_44x */



66:	li	r3,-ENOSYS

	b	ret_from_syscall
@@ -683,6 +696,16 @@ resume_kernel: 


	/* interrupts are hard-disabled at this point */

restore:

#ifdef CONFIG_44x

	lis	r4,icache_44x_need_flush@ha

	lwz	r5,icache_44x_need_flush@l(r4)

	cmplwi	cr0,r5,0

	beq+	1f

	li	r6,0

	iccci	r0,r0

	stw	r6,icache_44x_need_flush@l(r4)

1:

#endif  /* CONFIG_44x */

	lwz	r0,GPR0(r1)

	lwz	r2,GPR2(r1)

	REST_4GPRS(3, r1)

arch/powerpc/kernel/misc_32.S

+9 −0
Original line number Diff line number Diff line
@@ -543,12 +543,21 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 
	addi	r3,r3,L1_CACHE_BYTES

	bdnz	0b

	sync

#ifndef CONFIG_44x

	/* We don't flush the icache on 44x. Those have a virtual icache

	 * and we don't have access to the virtual address here (it's

	 * not the page vaddr but where it's mapped in user space). The

	 * flushing of the icache on these is handled elsewhere, when

	 * a change in the address space occurs, before returning to

	 * user space

	 */

	mtctr	r4

1:	icbi	0,r6

	addi	r6,r6,L1_CACHE_BYTES

	bdnz	1b

	sync

	isync

#endif /* CONFIG_44x */

	blr



/*

arch/powerpc/mm/44x_mmu.c

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
 */

unsigned int tlb_44x_index; /* = 0 */

unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;

int icache_44x_need_flush;



/*

 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem

arch/ppc/kernel/entry.S

+23 −0
Original line number Diff line number Diff line
@@ -244,6 +244,13 @@ syscall_exit_cont: 
	andis.	r10,r0,DBCR0_IC@h

	bnel-	load_dbcr0

#endif

#ifdef CONFIG_44x

	lis	r4,icache_44x_need_flush@ha

	lwz	r5,icache_44x_need_flush@l(r4)

	cmplwi	cr0,r5,0

	bne-	2f

1:

#endif /* CONFIG_44x */

	stwcx.	r0,0,r1			/* to clear the reservation */

	lwz	r4,_LINK(r1)

	lwz	r5,_CCR(r1)
@@ -258,6 +265,12 @@ syscall_exit_cont: 
	mtspr	SPRN_SRR1,r8

	SYNC

	RFI

#ifdef CONFIG_44x

2:	li	r7,0

	iccci	r0,r0

	stw	r7,icache_44x_need_flush@l(r4)

	b	1b

#endif  /* CONFIG_44x */



66:	li	r3,-ENOSYS

	b	ret_from_syscall
@@ -679,6 +692,16 @@ resume_kernel: 


	/* interrupts are hard-disabled at this point */

restore:

#ifdef CONFIG_44x

	lis	r4,icache_44x_need_flush@ha

	lwz	r5,icache_44x_need_flush@l(r4)

	cmplwi	cr0,r5,0

	beq+	1f

	li	r6,0

	iccci	r0,r0

	stw	r6,icache_44x_need_flush@l(r4)

1:

#endif  /* CONFIG_44x */

	lwz	r0,GPR0(r1)

	lwz	r2,GPR2(r1)

	REST_4GPRS(3, r1)

arch/ppc/kernel/misc.S

+9 −0
Original line number Diff line number Diff line
@@ -499,12 +499,21 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 
	addi	r3,r3,L1_CACHE_BYTES

	bdnz	0b

	sync

#ifndef CONFIG_44x

	/* We don't flush the icache on 44x. Those have a virtual icache

	 * and we don't have access to the virtual address here (it's

	 * not the page vaddr but where it's mapped in user space). The

	 * flushing of the icache on these is handled elsewhere, when

	 * a change in the address space occurs, before returning to

	 * user space

	 */

	mtctr	r4

1:	icbi	0,r6

	addi	r6,r6,L1_CACHE_BYTES

	bdnz	1b

	sync

	isync

#endif /* CONFIG_44x */

	blr



/*

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