Merge branch 'upstream-linus' of git://github.com/jgarzik/libata-dev (b96d7157) · Commits · 戴 / test

drivers/ata/Kconfig

+2 −1

Original line number	Diff line number	Diff line
		@@ -820,7 +820,7 @@ config PATA_PLATFORM

		config PATA_OF_PLATFORM
		tristate "OpenFirmware platform device PATA support"
		depends on PATA_PLATFORM && PPC_OF
		depends on PATA_PLATFORM && OF
		help
		This option enables support for generic directly connected ATA
		devices commonly found on embedded systems with OpenFirmware
		@@ -831,6 +831,7 @@ config PATA_OF_PLATFORM
		config PATA_QDI
		tristate "QDI VLB PATA support"
		depends on ISA
		select PATA_LEGACY
		help
		Support for QDI 6500 and 6580 PATA controllers on VESA local bus.

drivers/ata/Makefile

+0 −1

Original line number	Diff line number	Diff line
		@@ -88,7 +88,6 @@ obj-$(CONFIG_PATA_PCMCIA) += pata_pcmcia.o
		obj-$(CONFIG_PATA_PALMLD) += pata_palmld.o
		obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o
		obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o
		obj-$(CONFIG_PATA_QDI) += pata_qdi.o
		obj-$(CONFIG_PATA_RB532) += pata_rb532_cf.o
		obj-$(CONFIG_PATA_RZ1000) += pata_rz1000.o
		obj-$(CONFIG_PATA_SAMSUNG_CF) += pata_samsung_cf.o

drivers/ata/ahci_platform.c

+38 −6

Original line number	Diff line number	Diff line
		@@ -23,20 +23,51 @@
		#include <linux/ahci_platform.h>
		#include "ahci.h"

		static struct scsi_host_template ahci_platform_sht = {
		AHCI_SHT("ahci_platform"),
		enum ahci_type {
		AHCI, /* standard platform ahci */
		IMX53_AHCI, /* ahci on i.mx53 */
		};

		static int __init ahci_probe(struct platform_device *pdev)
		static struct platform_device_id ahci_devtype[] = {
		{
		struct device *dev = &pdev->dev;
		struct ahci_platform_data *pdata = dev->platform_data;
		struct ata_port_info pi = {
		.name = "ahci",
		.driver_data = AHCI,
		}, {
		.name = "imx53-ahci",
		.driver_data = IMX53_AHCI,
		}, {
		/* sentinel */
		}
		};
		MODULE_DEVICE_TABLE(platform, ahci_devtype);


		static const struct ata_port_info ahci_port_info[] = {
		/* by features */
		[AHCI] = {
		.flags = AHCI_FLAG_COMMON,
		.pio_mask = ATA_PIO4,
		.udma_mask = ATA_UDMA6,
		.port_ops = &ahci_ops,
		},
		[IMX53_AHCI] = {
		.flags = AHCI_FLAG_COMMON,
		.pio_mask = ATA_PIO4,
		.udma_mask = ATA_UDMA6,
		.port_ops = &ahci_pmp_retry_srst_ops,
		},
		};

		static struct scsi_host_template ahci_platform_sht = {
		AHCI_SHT("ahci_platform"),
		};

		static int __init ahci_probe(struct platform_device *pdev)
		{
		struct device *dev = &pdev->dev;
		struct ahci_platform_data *pdata = dev->platform_data;
		const struct platform_device_id *id = platform_get_device_id(pdev);
		struct ata_port_info pi = ahci_port_info[id->driver_data];
		const struct ata_port_info *ppi[] = { &pi, NULL };
		struct ahci_host_priv *hpriv;
		struct ata_host *host;
		@@ -177,6 +208,7 @@ static struct platform_driver ahci_driver = {
		.name = "ahci",
		.owner = THIS_MODULE,
		},
		.id_table = ahci_devtype,
		};

		static int __init ahci_init(void)

drivers/ata/ata_piix.c

+73 −80

Original line number	Diff line number	Diff line
		@@ -113,6 +113,8 @@ enum {
		PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
		PIIX_SATA_FLAGS = ATA_FLAG_SATA \| PIIX_FLAG_CHECKINTR,

		PIIX_FLAG_PIO16 = (1 << 30), /support 16bit PIO only/

		PIIX_80C_PRI = (1 << 5) \| (1 << 4),
		PIIX_80C_SEC = (1 << 7) \| (1 << 6),

		@@ -147,6 +149,7 @@ enum piix_controller_ids {
		ich8m_apple_sata, /* locks up on second port enable */
		tolapai_sata,
		piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
		ich8_sata_snb,
		};

		struct piix_map_db {
		@@ -177,6 +180,7 @@ static int piix_sidpr_scr_write(struct ata_link *link,
		static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
		unsigned hints);
		static bool piix_irq_check(struct ata_port *ap);
		static int piix_port_start(struct ata_port *ap);
		#ifdef CONFIG_PM
		static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
		static int piix_pci_device_resume(struct pci_dev *pdev);
		@@ -298,21 +302,21 @@ static const struct pci_device_id piix_pci_tbl[] = {
		/* SATA Controller IDE (PCH) */
		{ 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
		/* SATA Controller IDE (CPT) */
		{ 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
		{ 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
		/* SATA Controller IDE (CPT) */
		{ 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
		{ 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
		/* SATA Controller IDE (CPT) */
		{ 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
		/* SATA Controller IDE (CPT) */
		{ 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
		/* SATA Controller IDE (PBG) */
		{ 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
		{ 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
		/* SATA Controller IDE (PBG) */
		{ 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
		/* SATA Controller IDE (Panther Point) */
		{ 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
		{ 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
		/* SATA Controller IDE (Panther Point) */
		{ 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
		{ 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
		/* SATA Controller IDE (Panther Point) */
		{ 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
		/* SATA Controller IDE (Panther Point) */
		@@ -338,6 +342,7 @@ static struct scsi_host_template piix_sht = {
		static struct ata_port_operations piix_sata_ops = {
		.inherits = &ata_bmdma32_port_ops,
		.sff_irq_check = piix_irq_check,
		.port_start = piix_port_start,
		};

		static struct ata_port_operations piix_pata_ops = {
		@@ -478,6 +483,7 @@ static const struct piix_map_db *piix_map_db_table[] = {
		[ich8_2port_sata] = &ich8_2port_map_db,
		[ich8m_apple_sata] = &ich8m_apple_map_db,
		[tolapai_sata] = &tolapai_map_db,
		[ich8_sata_snb] = &ich8_map_db,
		};

		static struct ata_port_info piix_port_info[] = {
		@@ -606,6 +612,19 @@ static struct ata_port_info piix_port_info[] = {
		.port_ops = &piix_vmw_ops,
		},

		/*
		* some Sandybridge chipsets have broken 32 mode up to now,
		* see https://bugzilla.kernel.org/show_bug.cgi?id=40592
		*/
		[ich8_sata_snb] =
		{
		.flags = PIIX_SATA_FLAGS \| PIIX_FLAG_SIDPR \| PIIX_FLAG_PIO16,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA6,
		.port_ops = &piix_sata_ops,
		},

		};

		static struct pci_bits piix_enable_bits[] = {
		@@ -649,6 +668,14 @@ static const struct ich_laptop ich_laptop[] = {
		{ 0, }
		};

		static int piix_port_start(struct ata_port *ap)
		{
		if (!(ap->flags & PIIX_FLAG_PIO16))
		ap->pflags \|= ATA_PFLAG_PIO32 \| ATA_PFLAG_PIO32CHANGE;

		return ata_bmdma_port_start(ap);
		}

		/**
		* ich_pata_cable_detect - Probe host controller cable detect info
		* @ap: Port for which cable detect info is desired
		@@ -704,22 +731,11 @@ static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)

		static DEFINE_SPINLOCK(piix_lock);

		/**
		* piix_set_piomode - Initialize host controller PATA PIO timings
		* @ap: Port whose timings we are configuring
		* @adev: um
		*
		* Set PIO mode for device, in host controller PCI config space.
		*
		* LOCKING:
		* None (inherited from caller).
		*/

		static void piix_set_piomode(struct ata_port ap, struct ata_device adev)
		static void piix_set_timings(struct ata_port ap, struct ata_device adev,
		u8 pio)
		{
		struct pci_dev *dev = to_pci_dev(ap->host->dev);
		unsigned long flags;
		unsigned int pio = adev->pio_mode - XFER_PIO_0;
		unsigned int is_slave = (adev->devno != 0);
		unsigned int master_port= ap->port_no ? 0x42 : 0x40;
		unsigned int slave_port = 0x44;
		@@ -744,10 +760,16 @@ static void piix_set_piomode(struct ata_port ap, struct ata_device adev)
		control \|= 1; /* TIME1 enable */
		if (ata_pio_need_iordy(adev))
		control \|= 2; /* IE enable */

		/* Intel specifies that the PPE functionality is for disk only */
		if (adev->class == ATA_DEV_ATA)
		control \|= 4; /* PPE enable */
		/*
		* If the drive MWDMA is faster than it can do PIO then
		* we must force PIO into PIO0
		*/
		if (adev->pio_mode < XFER_PIO_0 + pio)
		/* Enable DMA timing only */
		control \|= 8; /* PIO cycles in PIO0 */

		spin_lock_irqsave(&piix_lock, flags);

		@@ -759,8 +781,6 @@ static void piix_set_piomode(struct ata_port ap, struct ata_device adev)
		if (is_slave) {
		/* clear TIME1\|IE1\|PPE1\|DTE1 */
		master_data &= 0xff0f;
		/* Enable SITRE (separate slave timing register) */
		master_data \|= 0x4000;
		/* enable PPE1, IE1 and TIME1 as needed */
		master_data \|= (control << 4);
		pci_read_config_byte(dev, slave_port, &slave_data);
		@@ -778,6 +798,9 @@ static void piix_set_piomode(struct ata_port ap, struct ata_device adev)
		(timings[pio][0] << 12) \|
		(timings[pio][1] << 8);
		}

		/* Enable SITRE (separate slave timing register) */
		master_data \|= 0x4000;
		pci_write_config_word(dev, master_port, master_data);
		if (is_slave)
		pci_write_config_byte(dev, slave_port, slave_data);
		@@ -794,6 +817,22 @@ static void piix_set_piomode(struct ata_port ap, struct ata_device adev)
		spin_unlock_irqrestore(&piix_lock, flags);
		}

		/**
		* piix_set_piomode - Initialize host controller PATA PIO timings
		* @ap: Port whose timings we are configuring
		* @adev: Drive in question
		*
		* Set PIO mode for device, in host controller PCI config space.
		*
		* LOCKING:
		* None (inherited from caller).
		*/

		static void piix_set_piomode(struct ata_port ap, struct ata_device adev)
		{
		piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
		}

		/**
		* do_pata_set_dmamode - Initialize host controller PATA PIO timings
		* @ap: Port whose timings we are configuring
		@@ -810,31 +849,20 @@ static void do_pata_set_dmamode(struct ata_port ap, struct ata_device adev, in
		{
		struct pci_dev *dev = to_pci_dev(ap->host->dev);
		unsigned long flags;
		u8 master_port = ap->port_no ? 0x42 : 0x40;
		u16 master_data;
		u8 speed = adev->dma_mode;
		int devid = adev->devno + 2 * ap->port_no;
		u8 udma_enable = 0;

		static const /* ISP RTC */
		u8 timings[][2] = { { 0, 0 },
		{ 0, 0 },
		{ 1, 0 },
		{ 2, 1 },
		{ 2, 3 }, };

		spin_lock_irqsave(&piix_lock, flags);

		pci_read_config_word(dev, master_port, &master_data);
		if (ap->udma_mask)
		pci_read_config_byte(dev, 0x48, &udma_enable);

		if (speed >= XFER_UDMA_0) {
		unsigned int udma = adev->dma_mode - XFER_UDMA_0;
		unsigned int udma = speed - XFER_UDMA_0;
		u16 udma_timing;
		u16 ideconf;
		int u_clock, u_speed;

		spin_lock_irqsave(&piix_lock, flags);

		pci_read_config_byte(dev, 0x48, &udma_enable);

		/*
		* UDMA is handled by a combination of clock switching and
		* selection of dividers
		@@ -867,56 +895,21 @@ static void do_pata_set_dmamode(struct ata_port ap, struct ata_device adev, in
		performance (WR_PingPong_En) */
		pci_write_config_word(dev, 0x54, ideconf);
		}

		pci_write_config_byte(dev, 0x48, udma_enable);

		spin_unlock_irqrestore(&piix_lock, flags);
		} else {
		/*
		* MWDMA is driven by the PIO timings. We must also enable
		* IORDY unconditionally along with TIME1. PPE has already
		* been set when the PIO timing was set.
		*/
		unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
		unsigned int control;
		u8 slave_data;
		/* MWDMA is driven by the PIO timings. */
		unsigned int mwdma = speed - XFER_MW_DMA_0;
		const unsigned int needed_pio[3] = {
		XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
		};
		int pio = needed_pio[mwdma] - XFER_PIO_0;

		control = 3; /* IORDY\|TIME1 */

		/* If the drive MWDMA is faster than it can do PIO then
		we must force PIO into PIO0 */

		if (adev->pio_mode < needed_pio[mwdma])
		/* Enable DMA timing only */
		control \|= 8; /* PIO cycles in PIO0 */

		if (adev->devno) { /* Slave */
		master_data &= 0xFF4F; /* Mask out IORDY\|TIME1\|DMAONLY */
		master_data \|= control << 4;
		pci_read_config_byte(dev, 0x44, &slave_data);
		slave_data &= (ap->port_no ? 0x0f : 0xf0);
		/* Load the matching timing */
		slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) << (ap->port_no ? 4 : 0);
		pci_write_config_byte(dev, 0x44, slave_data);
		} else { /* Master */
		master_data &= 0xCCF4; /* Mask out IORDY\|TIME1\|DMAONLY
		and master timing bits */
		master_data \|= control;
		master_data \|=
		(timings[pio][0] << 12) \|
		(timings[pio][1] << 8);
		/* XFER_PIO_0 is never used currently */
		piix_set_timings(ap, adev, pio);
		}

		if (ap->udma_mask)
		udma_enable &= ~(1 << devid);

		pci_write_config_word(dev, master_port, master_data);
		}
		/* Don't scribble on 0x48 if the controller does not support UDMA */
		if (ap->udma_mask)
		pci_write_config_byte(dev, 0x48, udma_enable);

		spin_unlock_irqrestore(&piix_lock, flags);
		}

		/**

drivers/ata/libata-core.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -2938,7 +2938,7 @@ int ata_timing_compute(struct ata_device *adev, unsigned short speed,
		if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
		memset(&p, 0, sizeof(p));

		if (speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
		if (speed >= XFER_PIO_0 && speed < XFER_SW_DMA_0) {
		if (speed <= XFER_PIO_2)
		p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
		else if ((speed <= XFER_PIO_4) \|\|

Admin message