MIPS: Use GENERIC_IOMAP (b962aeb0) · Commits · 戴 / test

arch/mips/Kconfig

+1 −1

Original line number	Diff line number	Diff line
		@@ -21,6 +21,7 @@ config MIPS
		select GENERIC_CLOCKEVENTS
		select GENERIC_CMOS_UPDATE
		select GENERIC_CPU_AUTOPROBE
		select GENERIC_IOMAP
		select GENERIC_IRQ_PROBE
		select GENERIC_IRQ_SHOW
		select GENERIC_LIB_ASHLDI3
		@@ -28,7 +29,6 @@ config MIPS
		select GENERIC_LIB_CMPDI2
		select GENERIC_LIB_LSHRDI3
		select GENERIC_LIB_UCMPDI2
		select GENERIC_PCI_IOMAP
		select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
		select GENERIC_SMP_IDLE_THREAD
		select GENERIC_TIME_VSYSCALL

arch/mips/include/asm/io.h

+10 −5

Original line number	Diff line number	Diff line
		@@ -79,6 +79,16 @@ static inline void set_io_port_base(unsigned long base)
		barrier();
		}

		/*
		* Provide the necessary definitions for generic iomap. We make use of
		* mips_io_port_base for iomap(), but we don't reserve any low addresses for
		* use with I/O ports.
		*/
		#define HAVE_ARCH_PIO_SIZE
		#define PIO_OFFSET mips_io_port_base
		#define PIO_MASK IO_SPACE_LIMIT
		#define PIO_RESERVED 0x0UL

		/*
		* Thanks to James van Artsdalen for a better timing-fix than
		* the two short jumps: using outb's to a nonexistent port seems
		@@ -172,11 +182,6 @@ static inline void *isa_bus_to_virt(unsigned long address)
		extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
		extern void __iounmap(const volatile void __iomem *addr);

		#ifndef CONFIG_PCI
		struct pci_dev;
		static inline void pci_iounmap(struct pci_dev dev, void __iomem addr) {}
		#endif

		static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
		unsigned long flags)
		{

arch/mips/lib/Makefile

+1 −1

Original line number	Diff line number	Diff line
		@@ -7,7 +7,7 @@ lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \
		mips-atomic.o strncpy_user.o \
		strnlen_user.o uncached.o

		obj-y += iomap.o iomap_copy.o
		obj-y += iomap_copy.o
		obj-$(CONFIG_PCI) += iomap-pci.o
		lib-$(CONFIG_GENERIC_CSUM) := $(filter-out csum_partial.o, $(lib-y))

arch/mips/lib/iomap-pci.c

+0 −7

Original line number	Diff line number	Diff line
		@@ -44,10 +44,3 @@ void __iomem __pci_ioport_map(struct pci_dev dev,
		}

		#endif /* CONFIG_PCI_DRIVERS_LEGACY */

		void pci_iounmap(struct pci_dev dev, void __iomem addr)
		{
		iounmap(addr);
		}

		EXPORT_SYMBOL(pci_iounmap);

arch/mips/lib/iomap.c

deleted100644 → 0

+0 −227

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0
		/*
		* Implement the default iomap interfaces
		*
		* (C) Copyright 2004 Linus Torvalds
		* (C) Copyright 2006 Ralf Baechle <ralf@linux-mips.org>
		* (C) Copyright 2007 MIPS Technologies, Inc.
		* written by Ralf Baechle <ralf@linux-mips.org>
		*/
		#include <linux/export.h>
		#include <asm/io.h>

		/*
		* Read/write from/to an (offsettable) iomem cookie. It might be a PIO
		* access or a MMIO access, these functions don't care. The info is
		* encoded in the hardware mapping set up by the mapping functions
		* (or the cookie itself, depending on implementation and hw).
		*
		* The generic routines don't assume any hardware mappings, and just
		* encode the PIO/MMIO as part of the cookie. They coldly assume that
		* the MMIO IO mappings are not in the low address range.
		*
		* Architectures for which this is not true can't use this generic
		* implementation and should do their own copy.
		*/

		#define PIO_MASK 0x0ffffUL

		unsigned int ioread8(void __iomem *addr)
		{
		return readb(addr);
		}

		EXPORT_SYMBOL(ioread8);

		unsigned int ioread16(void __iomem *addr)
		{
		return readw(addr);
		}

		EXPORT_SYMBOL(ioread16);

		unsigned int ioread16be(void __iomem *addr)
		{
		return be16_to_cpu(__raw_readw(addr));
		}

		EXPORT_SYMBOL(ioread16be);

		unsigned int ioread32(void __iomem *addr)
		{
		return readl(addr);
		}

		EXPORT_SYMBOL(ioread32);

		unsigned int ioread32be(void __iomem *addr)
		{
		return be32_to_cpu(__raw_readl(addr));
		}

		EXPORT_SYMBOL(ioread32be);

		void iowrite8(u8 val, void __iomem *addr)
		{
		writeb(val, addr);
		}

		EXPORT_SYMBOL(iowrite8);

		void iowrite16(u16 val, void __iomem *addr)
		{
		writew(val, addr);
		}

		EXPORT_SYMBOL(iowrite16);

		void iowrite16be(u16 val, void __iomem *addr)
		{
		__raw_writew(cpu_to_be16(val), addr);
		}

		EXPORT_SYMBOL(iowrite16be);

		void iowrite32(u32 val, void __iomem *addr)
		{
		writel(val, addr);
		}

		EXPORT_SYMBOL(iowrite32);

		void iowrite32be(u32 val, void __iomem *addr)
		{
		__raw_writel(cpu_to_be32(val), addr);
		}

		EXPORT_SYMBOL(iowrite32be);

		/*
		* These are the "repeat MMIO read/write" functions.
		* Note the "__mem" accesses, since we want to convert
		* to CPU byte order if the host bus happens to not match the
		* endianness of PCI/ISA (see mach-generic/mangle-port.h).
		*/
		static inline void mmio_insb(void __iomem addr, u8 dst, int count)
		{
		while (--count >= 0) {
		u8 data = __mem_readb(addr);
		*dst = data;
		dst++;
		}
		}

		static inline void mmio_insw(void __iomem addr, u16 dst, int count)
		{
		while (--count >= 0) {
		u16 data = __mem_readw(addr);
		*dst = data;
		dst++;
		}
		}

		static inline void mmio_insl(void __iomem addr, u32 dst, int count)
		{
		while (--count >= 0) {
		u32 data = __mem_readl(addr);
		*dst = data;
		dst++;
		}
		}

		static inline void mmio_outsb(void __iomem addr, const u8 src, int count)
		{
		while (--count >= 0) {
		__mem_writeb(*src, addr);
		src++;
		}
		}

		static inline void mmio_outsw(void __iomem addr, const u16 src, int count)
		{
		while (--count >= 0) {
		__mem_writew(*src, addr);
		src++;
		}
		}

		static inline void mmio_outsl(void __iomem addr, const u32 src, int count)
		{
		while (--count >= 0) {
		__mem_writel(*src, addr);
		src++;
		}
		}

		void ioread8_rep(void __iomem addr, void dst, unsigned long count)
		{
		mmio_insb(addr, dst, count);
		}

		EXPORT_SYMBOL(ioread8_rep);

		void ioread16_rep(void __iomem addr, void dst, unsigned long count)
		{
		mmio_insw(addr, dst, count);
		}

		EXPORT_SYMBOL(ioread16_rep);

		void ioread32_rep(void __iomem addr, void dst, unsigned long count)
		{
		mmio_insl(addr, dst, count);
		}

		EXPORT_SYMBOL(ioread32_rep);

		void iowrite8_rep(void __iomem addr, const void src, unsigned long count)
		{
		mmio_outsb(addr, src, count);
		}

		EXPORT_SYMBOL(iowrite8_rep);

		void iowrite16_rep(void __iomem addr, const void src, unsigned long count)
		{
		mmio_outsw(addr, src, count);
		}

		EXPORT_SYMBOL(iowrite16_rep);

		void iowrite32_rep(void __iomem addr, const void src, unsigned long count)
		{
		mmio_outsl(addr, src, count);
		}

		EXPORT_SYMBOL(iowrite32_rep);

		/*
		* Create a virtual mapping cookie for an IO port range
		*
		* This uses the same mapping are as the in/out family which has to be setup
		* by the platform initialization code.
		*
		* Just to make matters somewhat more interesting on MIPS systems with
		* multiple host bridge each will have it's own ioport address space.
		*/
		static void __iomem *ioport_map_legacy(unsigned long port, unsigned int nr)
		{
		return (void __iomem *) (mips_io_port_base + port);
		}

		void __iomem *ioport_map(unsigned long port, unsigned int nr)
		{
		if (port > PIO_MASK)
		return NULL;

		return ioport_map_legacy(port, nr);
		}

		EXPORT_SYMBOL(ioport_map);

		void ioport_unmap(void __iomem *addr)
		{
		/* Nothing to do */
		}

		EXPORT_SYMBOL(ioport_unmap);

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