drm/msm/a6xx: Remove unwanted regulator code (b94a6e37) · Commits · 戴 / test

The GMU code currently has some misguided code to try to work around a hardware quirk that requires the power domains on the GPU be collapsed in a certain order. Upcoming patches will do this the right way so get rid of the unused and unwanted regulator code. Signed-off-by:

Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by:

Rob Clark <robdclark@chromium.org>

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+0 −4

Original line number	Diff line number	Diff line
		@@ -681,9 +681,6 @@ int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu)
		gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
		(val & 1), 100, 1000);

		/* Force off the GX GSDC */
		regulator_force_disable(gmu->gx);

		/* Disable the resources */
		clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
		pm_runtime_put_sync(gmu->dev);
		@@ -1218,7 +1215,6 @@ int a6xx_gmu_probe(struct a6xx_gpu a6xx_gpu, struct device_node node)
		gmu->idle_level = GMU_IDLE_STATE_ACTIVE;

		pm_runtime_enable(gmu->dev);
		gmu->gx = devm_regulator_get(gmu->dev, "vdd");

		/* Get the list of clocks */
		ret = a6xx_gmu_clocks_probe(gmu);

drivers/gpu/drm/msm/adreno/a6xx_gmu.h

+0 −2

Original line number	Diff line number	Diff line
		@@ -52,8 +52,6 @@ struct a6xx_gmu {
		int hfi_irq;
		int gmu_irq;

		struct regulator *gx;

		struct iommu_domain *domain;
		u64 uncached_iova_base;

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