drm/i915/sideband: convert to using new struct drm_device logging macros (b908af55) · Commits · 戴 / test

drivers/gpu/drm/i915/intel_sideband.c

+17 −12

Original line number	Diff line number	Diff line
		@@ -105,7 +105,7 @@ static int vlv_sideband_rw(struct drm_i915_private *i915,
		if (intel_wait_for_register(uncore,
		VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
		5)) {
		DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
		drm_dbg(&i915->drm, "IOSF sideband idle wait (%s) timed out\n",
		is_read ? "read" : "write");
		return -EAGAIN;
		}
		@@ -129,7 +129,7 @@ static int vlv_sideband_rw(struct drm_i915_private *i915,
		*val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA);
		err = 0;
		} else {
		DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
		drm_dbg(&i915->drm, "IOSF sideband finish wait (%s) timed out\n",
		is_read ? "read" : "write");
		err = -ETIMEDOUT;
		}
		@@ -283,7 +283,8 @@ static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
		if (intel_wait_for_register_fw(uncore,
		SBI_CTL_STAT, SBI_BUSY, 0,
		100)) {
		DRM_ERROR("timeout waiting for SBI to become ready\n");
		drm_err(&i915->drm,
		"timeout waiting for SBI to become ready\n");
		return -EBUSY;
		}

		@@ -301,12 +302,13 @@ static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
		if (__intel_wait_for_register_fw(uncore,
		SBI_CTL_STAT, SBI_BUSY, 0,
		100, 100, &cmd)) {
		DRM_ERROR("timeout waiting for SBI to complete read\n");
		drm_err(&i915->drm,
		"timeout waiting for SBI to complete read\n");
		return -ETIMEDOUT;
		}

		if (cmd & SBI_RESPONSE_FAIL) {
		DRM_ERROR("error during SBI read of reg %x\n", reg);
		drm_err(&i915->drm, "error during SBI read of reg %x\n", reg);
		return -ENXIO;
		}

		@@ -426,7 +428,8 @@ int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
		mutex_unlock(&i915->sb_lock);

		if (err) {
		DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
		drm_dbg(&i915->drm,
		"warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
		mbox, __builtin_return_address(0), err);
		}

		@@ -447,7 +450,8 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
		mutex_unlock(&i915->sb_lock);

		if (err) {
		DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
		drm_dbg(&i915->drm,
		"warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
		val, mbox, __builtin_return_address(0), err);
		}

		@@ -519,7 +523,8 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
		* requests, and for any quirks of the PCODE firmware that delays
		* the request completion.
		*/
		DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
		drm_dbg_kms(&i915->drm,
		"PCODE timeout, retrying with preemption disabled\n");
		WARN_ON_ONCE(timeout_base_ms > 3);
		preempt_disable();
		ret = wait_for_atomic(COND, 50);

Admin message