Commit b8ccc593 authored by John Youn's avatar John Youn Committed by Felipe Balbi
Browse files

usb: dwc2: Reorder AHBIDLE and CSFTRST in dwc2_core_reset() 



According to the databook, the core soft reset should be done before
checking for AHBIDLE. The gadget version of core reset had it correct
but the hcd version did not. This fixes the hcd version.

Signed-off-by: default avatarJohn Youn <johnyoun@synopsys.com>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Tested-by: default avatarDouglas Anderson <dianders@chromium.org>
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent 7d56cc26

drivers/usb/dwc2/core.c

+9 −8
Original line number Diff line number Diff line
@@ -489,32 +489,33 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg) 


	dev_vdbg(hsotg->dev, "%s()\n", __func__);



	/* Wait for AHB master IDLE state */

	/* Core Soft Reset */

	greset = dwc2_readl(hsotg->regs + GRSTCTL);

	greset |= GRSTCTL_CSFTRST;

	dwc2_writel(greset, hsotg->regs + GRSTCTL);

	do {

		udelay(1);

		greset = dwc2_readl(hsotg->regs + GRSTCTL);

		if (++count > 50) {

			dev_warn(hsotg->dev,

				 "%s() HANG! AHB Idle GRSTCTL=%0x\n",

				 "%s() HANG! Soft Reset GRSTCTL=%0x\n",

				 __func__, greset);

			return -EBUSY;

		}

	} while (!(greset & GRSTCTL_AHBIDLE));

	} while (greset & GRSTCTL_CSFTRST);



	/* Core Soft Reset */

	/* Wait for AHB master IDLE state */

	count = 0;

	greset |= GRSTCTL_CSFTRST;

	dwc2_writel(greset, hsotg->regs + GRSTCTL);

	do {

		udelay(1);

		greset = dwc2_readl(hsotg->regs + GRSTCTL);

		if (++count > 50) {

			dev_warn(hsotg->dev,

				 "%s() HANG! Soft Reset GRSTCTL=%0x\n",

				 "%s() HANG! AHB Idle GRSTCTL=%0x\n",

				 __func__, greset);

			return -EBUSY;

		}

	} while (greset & GRSTCTL_CSFTRST);

	} while (!(greset & GRSTCTL_AHBIDLE));



	if (hsotg->dr_mode == USB_DR_MODE_HOST) {

		gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);

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