Commit b8a55591 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pp: use soc15 common macros instead of vega10 specific 



pp_soc15.h is vega10 specific. Update powerplay code to use soc15 common
macros defined in soc15_common.h.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e6636ae1

drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

+3 −4
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ 
#include "rv_ppsmc.h"

#include "smu10_hwmgr.h"

#include "power_state.h"

#include "pp_soc15.h"

#include "soc15_common.h"



#define SMU10_MAX_DEEPSLEEP_DIVIDER_ID     5

#define SMU10_MINIMUM_ENGINE_CLOCK         800   /* 8Mhz, the low boundary of engine clock allowed on this chip */
@@ -947,9 +947,8 @@ static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simpl 


static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)

{

	uint32_t reg_offset = soc15_get_register_offset(THM_HWID, 0,

			mmTHM_TCON_CUR_TMP_BASE_IDX, mmTHM_TCON_CUR_TMP);

	uint32_t reg_value = cgs_read_register(hwmgr->device, reg_offset);

	struct amdgpu_device *adev = hwmgr->adev;

	uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);

	int cur_temp =

		(reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

+5 −11
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ 
#include "smu9.h"

#include "smu9_driver_if.h"

#include "vega10_inc.h"

#include "pp_soc15.h"

#include "soc15_common.h"

#include "pppcielanes.h"

#include "vega10_hwmgr.h"

#include "vega10_processpptables.h"
@@ -754,7 +754,6 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 
	uint32_t config_telemetry = 0;

	struct pp_atomfwctrl_voltage_table vol_table;

	struct amdgpu_device *adev = hwmgr->adev;

	uint32_t reg;



	data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);

	if (data == NULL)
@@ -860,10 +859,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 
			advanceFanControlParameters.usFanPWMMinLimit *

			hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;



	reg = soc15_get_register_offset(DF_HWID, 0,

			mmDF_CS_AON0_DramBaseAddress0_BASE_IDX,

			mmDF_CS_AON0_DramBaseAddress0);

	data->mem_channels = (cgs_read_register(hwmgr->device, reg) &

	data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &

			DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>

			DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;

	PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
@@ -3808,11 +3804,12 @@ static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr, 
static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,

			      void *value, int *size)

{

	struct amdgpu_device *adev = hwmgr->adev;

	uint32_t sclk_idx, mclk_idx, activity_percent = 0;

	struct vega10_hwmgr *data = hwmgr->backend;

	struct vega10_dpm_table *dpm_table = &data->dpm_table;

	int ret = 0;

	uint32_t reg, val_vid;

	uint32_t val_vid;



	switch (idx) {

	case AMDGPU_PP_SENSOR_GFX_SCLK:
@@ -3862,10 +3859,7 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, 
		}

		break;

	case AMDGPU_PP_SENSOR_VDDGFX:

		reg = soc15_get_register_offset(SMUIO_HWID, 0,

			mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX,

			mmSMUSVI0_PLANE0_CURRENTVID);

		val_vid = (cgs_read_register(hwmgr->device, reg) &

		val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) &

			SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >>

			SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;

		*((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c

+20 −30
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ 
#include "vega10_ppsmc.h"

#include "vega10_inc.h"

#include "pp_debug.h"

#include "pp_soc15.h"

#include "soc15_common.h"



static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] =

{
@@ -888,36 +888,36 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable) 
	if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) {

		if (PP_CAP(PHM_PlatformCaps_SQRamping)) {

			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL);

			data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);

			data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);

			data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);

			data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);

			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data);

		}



		if (PP_CAP(PHM_PlatformCaps_DBRamping)) {

			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL);

			data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);

			data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);

			data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);

			data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);

			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data);

		}



		if (PP_CAP(PHM_PlatformCaps_TDRamping)) {

			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL);

			data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);

			data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);

			data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);

			data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);

			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data);

		}



		if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {

			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL);

			data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);

			data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);

			data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);

			data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);

			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data);

		}



		if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {

			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL);

			data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);

			data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);

			data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);

			data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);

			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data);

		}

	}
@@ -933,17 +933,15 @@ static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) 
	struct amdgpu_device *adev = hwmgr->adev;

	int result;

	uint32_t num_se = 0, count, data;

	uint32_t reg;



	num_se = adev->gfx.config.max_shader_engines;



	adev->gfx.rlc.funcs->enter_safe_mode(adev);



	mutex_lock(&adev->grbm_idx_mutex);

	reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);

	for (count = 0; count < num_se; count++) {

		data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);

		cgs_write_register(hwmgr->device, reg, data);

		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);



		result =  vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);

		result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
@@ -958,7 +956,7 @@ static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) 
		if (0 != result)

			break;

	}

	cgs_write_register(hwmgr->device, reg, 0xE0000000);

	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);

	mutex_unlock(&adev->grbm_idx_mutex);



	vega10_didt_set_mask(hwmgr, true);
@@ -986,17 +984,15 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) 
	struct amdgpu_device *adev = hwmgr->adev;

	int result;

	uint32_t num_se = 0, count, data;

	uint32_t reg;



	num_se = adev->gfx.config.max_shader_engines;



	adev->gfx.rlc.funcs->enter_safe_mode(adev);



	mutex_lock(&adev->grbm_idx_mutex);

	reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);

	for (count = 0; count < num_se; count++) {

		data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);

		cgs_write_register(hwmgr->device, reg, data);

		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);



		result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);

		result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
@@ -1005,7 +1001,7 @@ static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) 
		if (0 != result)

			break;

	}

	cgs_write_register(hwmgr->device, reg, 0xE0000000);

	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);

	mutex_unlock(&adev->grbm_idx_mutex);



	vega10_didt_set_mask(hwmgr, true);
@@ -1049,17 +1045,15 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr) 
	struct amdgpu_device *adev = hwmgr->adev;

	int result;

	uint32_t num_se = 0, count, data;

	uint32_t reg;



	num_se = adev->gfx.config.max_shader_engines;



	adev->gfx.rlc.funcs->enter_safe_mode(adev);



	mutex_lock(&adev->grbm_idx_mutex);

	reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);

	for (count = 0; count < num_se; count++) {

		data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);

		cgs_write_register(hwmgr->device, reg, data);

		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);

		result = vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);

		result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);

		result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
@@ -1070,7 +1064,7 @@ static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr) 
		if (0 != result)

			break;

	}

	cgs_write_register(hwmgr->device, reg, 0xE0000000);

	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);

	mutex_unlock(&adev->grbm_idx_mutex);



	vega10_didt_set_mask(hwmgr, true);
@@ -1099,7 +1093,6 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) 
	int result;

	uint32_t num_se = 0;

	uint32_t count, data;

	uint32_t reg;



	num_se = adev->gfx.config.max_shader_engines;
@@ -1108,10 +1101,9 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) 
	vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);



	mutex_lock(&adev->grbm_idx_mutex);

	reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);

	for (count = 0; count < num_se; count++) {

		data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);

		cgs_write_register(hwmgr->device, reg, data);

		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);

		result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);

		result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);

		result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
@@ -1120,7 +1112,7 @@ static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) 
		if (0 != result)

			break;

	}

	cgs_write_register(hwmgr->device, reg, 0xE0000000);

	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);

	mutex_unlock(&adev->grbm_idx_mutex);



	vega10_didt_set_mask(hwmgr, true);
@@ -1165,14 +1157,12 @@ static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) 
static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)

{

	struct amdgpu_device *adev = hwmgr->adev;

	uint32_t reg;

	int result;



	adev->gfx.rlc.funcs->enter_safe_mode(adev);



	mutex_lock(&adev->grbm_idx_mutex);

	reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);

	cgs_write_register(hwmgr->device, reg, 0xE0000000);

	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);

	mutex_unlock(&adev->grbm_idx_mutex);



	result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c

+41 −66
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ 
#include "vega10_hwmgr.h"

#include "vega10_ppsmc.h"

#include "vega10_inc.h"

#include "pp_soc15.h"

#include "soc15_common.h"

#include "pp_debug.h"



static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
@@ -89,6 +89,7 @@ int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, 


int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)

{

	struct amdgpu_device *adev = hwmgr->adev;

	struct vega10_hwmgr *data = hwmgr->backend;

	uint32_t tach_period;

	uint32_t crystal_clock_freq;
@@ -100,10 +101,8 @@ int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) 
	if (data->smu_features[GNLD_FAN_CONTROL].supported) {

		result = vega10_get_current_rpm(hwmgr, speed);

	} else {

		uint32_t reg = soc15_get_register_offset(THM_HWID, 0,

				mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);

		tach_period =

			CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),

			REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),

					  CG_TACH_STATUS,

					  TACH_PERIOD);
@@ -127,26 +126,23 @@ int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) 
*/

int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)

{

	uint32_t reg;



	reg = soc15_get_register_offset(THM_HWID, 0,

			mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);

	struct amdgpu_device *adev = hwmgr->adev;



	if (hwmgr->fan_ctrl_is_in_default_mode) {

		hwmgr->fan_ctrl_default_mode =

			CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),

			REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

				CG_FDO_CTRL2, FDO_PWM_MODE);

		hwmgr->tmin =

			CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),

			REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

				CG_FDO_CTRL2, TMIN);

		hwmgr->fan_ctrl_is_in_default_mode = false;

	}



	cgs_write_register(hwmgr->device, reg,

			CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),

	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,

			REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

				CG_FDO_CTRL2, TMIN, 0));

	cgs_write_register(hwmgr->device, reg,

			CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),

	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,

			REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

				CG_FDO_CTRL2, FDO_PWM_MODE, mode));



	return 0;
@@ -159,18 +155,15 @@ int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 
*/

int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)

{

	uint32_t reg;



	reg = soc15_get_register_offset(THM_HWID, 0,

			mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);

	struct amdgpu_device *adev = hwmgr->adev;



	if (!hwmgr->fan_ctrl_is_in_default_mode) {

		cgs_write_register(hwmgr->device, reg,

			CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),

		WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,

			REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

				CG_FDO_CTRL2, FDO_PWM_MODE,

				hwmgr->fan_ctrl_default_mode));

		cgs_write_register(hwmgr->device, reg,

			CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),

		WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,

			REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

				CG_FDO_CTRL2, TMIN,

				hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));

		hwmgr->fan_ctrl_is_in_default_mode = true;
@@ -257,10 +250,10 @@ int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) 
int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,

		uint32_t speed)

{

	struct amdgpu_device *adev = hwmgr->adev;

	uint32_t duty100;

	uint32_t duty;

	uint64_t tmp64;

	uint32_t reg;



	if (hwmgr->thermal_controller.fanInfo.bNoFan)

		return 0;
@@ -271,10 +264,7 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, 
	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))

		vega10_fan_ctrl_stop_smc_fan_control(hwmgr);



	reg = soc15_get_register_offset(THM_HWID, 0,

			mmCG_FDO_CTRL1_BASE_IDX, mmCG_FDO_CTRL1);



	duty100 = CGS_REG_GET_FIELD(cgs_read_register(hwmgr->device, reg),

	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),

				    CG_FDO_CTRL1, FMAX_DUTY100);



	if (duty100 == 0)
@@ -284,10 +274,8 @@ int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, 
	do_div(tmp64, 100);

	duty = (uint32_t)tmp64;



	reg = soc15_get_register_offset(THM_HWID, 0,

			mmCG_FDO_CTRL0_BASE_IDX, mmCG_FDO_CTRL0);

	cgs_write_register(hwmgr->device, reg,

		CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),

	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,

		REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),

			CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));



	return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
@@ -317,10 +305,10 @@ int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) 
*/

int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)

{

	struct amdgpu_device *adev = hwmgr->adev;

	uint32_t tach_period;

	uint32_t crystal_clock_freq;

	int result = 0;

	uint32_t reg;



	if (hwmgr->thermal_controller.fanInfo.bNoFan ||

	    (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
@@ -333,10 +321,8 @@ int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) 
	if (!result) {

		crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);

		tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);

		reg = soc15_get_register_offset(THM_HWID, 0,

				mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);

		cgs_write_register(hwmgr->device, reg,

				CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),

		WREG32_SOC15(THM, 0, mmCG_TACH_STATUS,

				REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),

					CG_TACH_STATUS, TACH_PERIOD,

					tach_period));

	}
@@ -350,13 +336,10 @@ int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) 
*/

int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)

{

	struct amdgpu_device *adev = hwmgr->adev;

	int temp;

	uint32_t reg;



	reg = soc15_get_register_offset(THM_HWID, 0,

			mmCG_MULT_THERMAL_STATUS_BASE_IDX,  mmCG_MULT_THERMAL_STATUS);



	temp = cgs_read_register(hwmgr->device, reg);

	temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);



	temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>

			CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
@@ -379,11 +362,12 @@ int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr) 
static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,

		struct PP_TemperatureRange *range)

{

	struct amdgpu_device *adev = hwmgr->adev;

	int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *

			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;

	int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *

			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;

	uint32_t val, reg;

	uint32_t val;



	if (low < range->min)

		low = range->min;
@@ -393,20 +377,17 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, 
	if (low > high)

		return -EINVAL;



	reg = soc15_get_register_offset(THM_HWID, 0,

			mmTHM_THERMAL_INT_CTRL_BASE_IDX, mmTHM_THERMAL_INT_CTRL);



	val = cgs_read_register(hwmgr->device, reg);

	val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);



	val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

	val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

	val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));

	val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));

	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));

	val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &

			(~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &

			(~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);



	cgs_write_register(hwmgr->device, reg, val);

	WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);



	return 0;

}
@@ -418,21 +399,17 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, 
*/

static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)

{

	uint32_t reg;

	struct amdgpu_device *adev = hwmgr->adev;



	if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {

		reg = soc15_get_register_offset(THM_HWID, 0,

				mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL);

		cgs_write_register(hwmgr->device, reg,

			CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),

		WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,

			REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

				CG_TACH_CTRL, EDGE_PER_REV,

				hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1));

	}



	reg = soc15_get_register_offset(THM_HWID, 0,

			mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);

	cgs_write_register(hwmgr->device, reg,

		CGS_REG_SET_FIELD(cgs_read_register(hwmgr->device, reg),

	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,

		REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),

			CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28));



	return 0;
@@ -445,9 +422,9 @@ static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr) 
*/

static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)

{

	struct amdgpu_device *adev = hwmgr->adev;

	struct vega10_hwmgr *data = hwmgr->backend;

	uint32_t val = 0;

	uint32_t reg;



	if (data->smu_features[GNLD_FW_CTF].supported) {

		if (data->smu_features[GNLD_FW_CTF].enabled)
@@ -465,8 +442,7 @@ static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr) 
	val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);

	val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);



	reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);

	cgs_write_register(hwmgr->device, reg, val);

	WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);



	return 0;

}
@@ -477,8 +453,8 @@ static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr) 
*/

int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)

{

	struct amdgpu_device *adev = hwmgr->adev;

	struct vega10_hwmgr *data = hwmgr->backend;

	uint32_t reg;



	if (data->smu_features[GNLD_FW_CTF].supported) {

		if (!data->smu_features[GNLD_FW_CTF].enabled)
@@ -493,8 +469,7 @@ int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr) 
		data->smu_features[GNLD_FW_CTF].enabled = false;

	}



	reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);

	cgs_write_register(hwmgr->device, reg, 0);

	WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);



	return 0;

}

drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

+0 −1
Original line number Diff line number Diff line
@@ -34,7 +34,6 @@ 
#include "atomfirmware.h"

#include "cgs_common.h"

#include "vega12_inc.h"

#include "pp_soc15.h"

#include "pppcielanes.h"

#include "vega12_hwmgr.h"

#include "vega12_processpptables.h"

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