drm/i915: Use indirect ctx bb to mend CMD_BUF_CCTL (b8a11811) · Commits · 戴 / test

drivers/gpu/drm/i915/gt/intel_lrc.c

+109 −3

Original line number	Diff line number	Diff line
		@@ -294,6 +294,19 @@ static int lrc_ring_indirect_offset(const struct intel_engine_cs *engine)
		return x + 2;
		}

		static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
		{
		if (engine->class != RENDER_CLASS)
		return -1;

		if (INTEL_GEN(engine->i915) >= 12)
		return 0xb6;
		else if (INTEL_GEN(engine->i915) >= 11)
		return 0xaa;
		else
		return -1;
		}

		static u32
		lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
		{
		@@ -607,7 +620,7 @@ static void set_offsets(u32 *regs,
		#define REG16(x) \
		(((x) >> 9) \| BIT(7) \| BUILD_BUG_ON_ZERO(x >= 0x10000)), \
		(((x) >> 2) & 0x7f)
		#define END(x) 0, (x)
		#define END(total_state_size) 0, (total_state_size)
		{
		const u32 base = engine->mmio_base;

		@@ -1015,8 +1028,63 @@ static const u8 gen12_rcs_offsets[] = {
		NOP(6),
		LRI(1, 0),
		REG(0x0c8),
		NOP(3 + 9 + 1),

		LRI(51, POSTED),
		REG16(0x588),
		REG16(0x588),
		REG16(0x588),
		REG16(0x588),
		REG16(0x588),
		REG16(0x588),
		REG(0x028),
		REG(0x09c),
		REG(0x0c0),
		REG(0x178),
		REG(0x17c),
		REG16(0x358),
		REG(0x170),
		REG(0x150),
		REG(0x154),
		REG(0x158),
		REG16(0x41c),
		REG16(0x600),
		REG16(0x604),
		REG16(0x608),
		REG16(0x60c),
		REG16(0x610),
		REG16(0x614),
		REG16(0x618),
		REG16(0x61c),
		REG16(0x620),
		REG16(0x624),
		REG16(0x628),
		REG16(0x62c),
		REG16(0x630),
		REG16(0x634),
		REG16(0x638),
		REG16(0x63c),
		REG16(0x640),
		REG16(0x644),
		REG16(0x648),
		REG16(0x64c),
		REG16(0x650),
		REG16(0x654),
		REG16(0x658),
		REG16(0x65c),
		REG16(0x660),
		REG16(0x664),
		REG16(0x668),
		REG16(0x66c),
		REG16(0x670),
		REG16(0x674),
		REG16(0x678),
		REG16(0x67c),
		REG(0x068),
		REG(0x084),
		NOP(1),

		END(80)
		END(192)
		};

		#undef END
		@@ -3246,6 +3314,38 @@ gen12_emit_restore_scratch(const struct intel_context ce, u32 cs)
		return cs;
		}

		static u32 *
		gen12_emit_cmd_buf_wa(const struct intel_context ce, u32 cs)
		{
		GEM_BUG_ON(lrc_ring_cmd_buf_cctl(ce->engine) == -1);

		*cs++ = MI_LOAD_REGISTER_MEM_GEN8 \|
		MI_SRM_LRM_GLOBAL_GTT \|
		MI_LRI_LRM_CS_MMIO;
		*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
		*cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +
		(lrc_ring_cmd_buf_cctl(ce->engine) + 1) * sizeof(u32);
		*cs++ = 0;

		*cs++ = MI_LOAD_REGISTER_REG \|
		MI_LRR_SOURCE_CS_MMIO \|
		MI_LRI_LRM_CS_MMIO;
		*cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
		*cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0));

		return cs;
		}

		static u32 *
		gen12_emit_indirect_ctx_rcs(const struct intel_context ce, u32 cs)
		{
		cs = gen12_emit_timestamp_wa(ce, cs);
		cs = gen12_emit_cmd_buf_wa(ce, cs);
		cs = gen12_emit_restore_scratch(ce, cs);

		return cs;
		}

		static u32 *
		gen12_emit_indirect_ctx_xcs(const struct intel_context ce, u32 cs)
		{
		@@ -3317,9 +3417,15 @@ __execlists_update_reg_state(const struct intel_context *ce,
		}

		if (ce->wa_bb_page) {
		u32 (fn)(const struct intel_context ce, u32 cs);

		fn = gen12_emit_indirect_ctx_xcs;
		if (ce->engine->class == RENDER_CLASS)
		fn = gen12_emit_indirect_ctx_rcs;

		/* Mutually exclusive wrt to global indirect bb */
		GEM_BUG_ON(engine->wa_ctx.indirect_ctx.size);
		setup_indirect_ctx_bb(ce, engine, gen12_emit_indirect_ctx_xcs);
		setup_indirect_ctx_bb(ce, engine, fn);
		}
		}

drivers/gpu/drm/i915/gt/selftest_lrc.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -4618,6 +4618,11 @@ static int live_lrc_fixed(void *arg)
		lrc_ring_gpr0(engine),
		"RING_CS_GPR0"
		},
		{
		i915_mmio_reg_offset(RING_CMD_BUF_CCTL(engine->mmio_base)),
		lrc_ring_cmd_buf_cctl(engine),
		"RING_CMD_BUF_CCTL"
		},
		{ },
		}, *t;
		u32 *hw;

drivers/gpu/drm/i915/i915_reg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -2657,6 +2657,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
		#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */
		#define RING_INSTPM(base) _MMIO((base) + 0xc0)
		#define RING_MI_MODE(base) _MMIO((base) + 0x9c)
		#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
		#define INSTPS _MMIO(0x2070) /* 965+ only */
		#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
		#define ACTHD_I965 _MMIO(0x2074)

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