ARCv2: barriers

generic-y += auxvec.h

generic-y += barrier.h

generic-y += bitsperlong.h

generic-y += bugs.h

generic-y += clkdev.h

/*

 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

#ifndef __ASM_BARRIER_H

#define __ASM_BARRIER_H

#ifdef CONFIG_ISA_ARCV2

/*

 * ARCv2 based HS38 cores are in-order issue, but still weakly ordered

 * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...

 *

 * Explicit barrier provided by DMB instruction

 *  - Operand supports fine grained load/store/load+store semantics

 *  - Ensures that selected memory operation issued before it will complete

 *    before any subsequent memory operation of same type

 *  - DMB guarantees SMP as well as local barrier semantics

 *    (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.

 *    UP: barrier(), SMP: smp_*mb == *mb)

 *  - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed

 *    in the general case. Plus it only provides full barrier.

 */

#define mb()	asm volatile("dmb 3\n" : : : "memory")

#define rmb()	asm volatile("dmb 1\n" : : : "memory")

#define wmb()	asm volatile("dmb 2\n" : : : "memory")

#endif

#ifdef CONFIG_ISA_ARCOMPACT

/*

 * ARCompact based cores (ARC700) only have SYNC instruction which is super

 * heavy weight as it flushes the pipeline as well.

 * There are no real SMP implementations of such cores.

 */

#define mb()	asm volatile("sync\n" : : : "memory")

#endif

#include <asm-generic/barrier.h>

#endif

}

#define readb_relaxed readb

#define readw_relaxed readw

#define readl_relaxed readl

#ifdef CONFIG_ISA_ARCV2

#include <asm/barrier.h>

#define __iormb()		rmb()

#define __iowmb()		wmb()

#else

#define __iormb()		do { } while (0)

#define __iowmb()		do { } while (0)

#endif

/*

 * MMIO can also get buffered/optimized in micro-arch, so barriers needed

 * Based on ARM model for the typical use case

 *

 *	<ST [DMA buffer]>

 *	<writel MMIO "go" reg>

 *  or:

 *	<readl MMIO "status" reg>

 *	<LD [DMA buffer]>

 *

 * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com

 */

#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(); __v; })

#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(); __v; })

#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(); __v; })

#define writeb(v,c)		({ __iowmb(); writeb_relaxed(v,c); })

#define writew(v,c)		({ __iowmb(); writew_relaxed(v,c); })

#define writel(v,c)		({ __iowmb(); writel_relaxed(v,c); })

/*

 * Relaxed API for drivers which can handle any ordering themselves

 */

#define readb_relaxed(c)	__raw_readb(c)

#define readw_relaxed(c)	__raw_readw(c)

#define readl_relaxed(c)	__raw_readl(c)

#define writeb_relaxed(v,c)	__raw_writeb(v,c)

#define writew_relaxed(v,c)	__raw_writew(v,c)

#define writel_relaxed(v,c)	__raw_writel(v,c)

#include <asm-generic/io.h>