Commit b8969ef5 authored by Kevin Hilman's avatar Kevin Hilman
Browse files

Merge branch 'soc/sched_clock' into next/soc



From Stephen Boyd:
* soc/sched_clock:
  ARM: versatile: Switch to sched_clock_register()
  ARM: orion: Switch to sched_clock_register()
  ARM: OMAP: Switch to sched_clock_register()
  ARM: iop: Switch to sched_clock_register()
  ARM: u300: Switch to sched_clock_register()
  ARM: sa1100: Switch to sched_clock_register()
  ARM: pxa: Switch to sched_clock_register()
  ARM: OMAP2+: Switch to sched_clock_register()
  ARM: OMAP1: Switch to sched_clock_register()
  ARM: msm: Switch to sched_clock_register()
  ARM: mmp: Switch to sched_clock_register()
  ARM: IXP4xx: Switch to sched_clock_register()
  ARM: integrator: Switch to sched_clock_register()
  ARM: imx: Switch to sched_clock_register()
  ARM: davinci: Switch to sched_clock_register()
  ARM: clps711x: Switch to sched_clock_register()
  ARM: timer-sp: Switch to sched_clock_register()

Signed-off-by: default avatarKevin Hilman <khilman@linaro.org>
parents b19e11fb d25f1d5a
Loading
Loading
Loading
Loading
+2 −2
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ static long __init sp804_get_clock_rate(struct clk *clk)

static void __iomem *sched_clock_base;

static u32 sp804_read(void)
static u64 notrace sp804_read(void)
{
	return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
}
@@ -104,7 +104,7 @@ void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,

	if (use_sched_clock) {
		sched_clock_base = base;
		setup_sched_clock(sp804_read, 32, rate);
		sched_clock_register(sp804_read, 32, rate);
	}
}

+2 −2
Original line number Diff line number Diff line
@@ -259,7 +259,7 @@ asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
	} while (1);
}

static u32 notrace clps711x_sched_clock_read(void)
static u64 notrace clps711x_sched_clock_read(void)
{
	return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
}
@@ -366,7 +366,7 @@ void __init clps711x_timer_init(void)
	tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
	clps_writel(tmp, SYSCON1);

	setup_sched_clock(clps711x_sched_clock_read, 16, timl);
	sched_clock_register(clps711x_sched_clock_read, 16, timl);

	clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
			      "clps711x_clocksource", timl, 300, 16,
+2 −2
Original line number Diff line number Diff line
@@ -285,7 +285,7 @@ static struct clocksource clocksource_davinci = {
/*
 * Overwrite weak default sched_clock with something more precise
 */
static u32 notrace davinci_read_sched_clock(void)
static u64 notrace davinci_read_sched_clock(void)
{
	return timer32_read(&timers[TID_CLOCKSOURCE]);
}
@@ -391,7 +391,7 @@ void __init davinci_timer_init(void)
				    davinci_clock_tick_rate))
		printk(err, clocksource_davinci.name);

	setup_sched_clock(davinci_read_sched_clock, 32,
	sched_clock_register(davinci_read_sched_clock, 32,
			  davinci_clock_tick_rate);

	/* setup clockevent */
+2 −2
Original line number Diff line number Diff line
@@ -111,7 +111,7 @@ static void gpt_irq_acknowledge(void)

static void __iomem *sched_clock_reg;

static u32 notrace mxc_read_sched_clock(void)
static u64 notrace mxc_read_sched_clock(void)
{
	return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
}
@@ -123,7 +123,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)

	sched_clock_reg = reg;

	setup_sched_clock(mxc_read_sched_clock, 32, c);
	sched_clock_register(mxc_read_sched_clock, 32, c);
	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
			clocksource_mmio_readl_up);
}
+2 −2
Original line number Diff line number Diff line
@@ -277,7 +277,7 @@ struct amba_pl010_data ap_uart_data = {

static unsigned long timer_reload;

static u32 notrace integrator_read_sched_clock(void)
static u64 notrace integrator_read_sched_clock(void)
{
	return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
}
@@ -298,7 +298,7 @@ static void integrator_clocksource_init(unsigned long inrate,

	clocksource_mmio_init(base + TIMER_VALUE, "timer2",
			rate, 200, 16, clocksource_mmio_readl_down);
	setup_sched_clock(integrator_read_sched_clock, 16, rate);
	sched_clock_register(integrator_read_sched_clock, 16, rate);
}

static void __iomem * clkevt_base;
Loading